comp.v

来自「精通VerilogHDL：IC设计核心技术实例详解」· Verilog 代码 · 共 14 行

`timescale 1ns/10ps
`define raw_bits 0 
    
module comp(a1,a2,min,max);
input  [`raw_bits+3:0] a1,a2;
output [`raw_bits+3:0] min,max;
wire  [`raw_bits+3:0] min,max;

wire a1_bigger_than_a2=(a1>=a2);
assign min=(a1_bigger_than_a2)? a2:a1;
assign max=(a1_bigger_than_a2)? a1:a2;


endmodule