top.v

精通VerilogHDL：IC设计核心技术实例详解

`timescale 1ns/10ps   
module top;

reg clk=0,nrst=0,mul_en=0;
reg  [15:0] temp;
 
wire [15:0] product; 
wire oen;
always #20 clk=~clk;
initial
begin  
  #41  nrst=0;
  #85  nrst=1;
  #250 ;
  @(posedge clk)
  #1   mul_en=1;
end

always@(posedge clk or negedge nrst)
 if (~nrst) begin
    temp<=0;  
 end else if (mul_en&oen) begin  
    temp<=#1 temp+1;
 end   

mul mul( //input
          .clk    (clk),
          .nrst   (nrst),
          .a      (temp[7:0]),
          .b      (temp[15:8]),
          .mul_en (mul_en),
         //output
          .oen    (oen),
          .product(product));  

reg [7:0] a_d,b_d;          
always@(posedge clk)
begin
   a_d<=temp[7:0];
   b_d<=temp[15:8];
end          

wire load=top.mul.load;          
wire err_found=load&(product!=(a_d*b_d));        
always@(negedge clk)
begin
 if (temp=={16{1'b1}} & load) begin
  $display("\nSimulation Passed!\n");
  #1500;
  $finish;  
 end else if (mul_en & load & err_found) begin          
  $display("product mismatch found at %t\n a=%d b=%d",$time,a_d,b_d);  
  $display("exact value=%d but get:%d",(a_d*b_d),product);
  #50;
  $stop;
 end 
end 
                 
initial
begin
  $dumpfile("./mul.vcd");    
  $dumpvars(0,top);          
end
endmodule