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V 的代码
dds.v
`include "romtab.v"
`include "claadd8s.v"
`include "loadfw.v"
`include "loadpw.v"
`include "sinlup.v"
`include "phasea.v"
`include "phasemod.v"
`include "pngen.v"
/**************************
romtab.v
/*******************************************************************************
****************************************************************************
**
mips.v
//-------------------------------------------------------
// mips.v
// Max Yi (byyi@hmc.edu) and David_Harris@hmc.edu 12/9/03
// Model of subset of MIPS processor described in Ch 1
//-------------
micro.v
//----------------------------------------------------------------------------
//
// Name: micro.v
//
// Description: Microprocessor simulation model for I2C serial controller
//
// $R
alu.v
/*
Daniel L. Rosenband
10/10/99
ALU
*/
module ALU (/*AUTOARG*/
// Outputs
IALU2MEM, ALUResult, ALUResultRegAddr, ALUResultUnlatched,
ALUResultRegAddrUnlatched, ALURtDataOu
memstage.v
/*
Daniel L. Rosenband
10/12/99
ALU
*/
module MemStage (/*AUTOARG*/
// Outputs
DMemAddr, DMemWE, DMemWriteData, MemResult, MemResultRegAddr,
MemResultUnlatched, MemResultRegAddrUnlat
pemips.v
/*
Daniel L. Rosenband
9/28/99
Empty PE
*/
module PEMIPS (/*AUTOARG*/
// Outputs
LeftMemUserOutData, LeftMemUserOutAddr, LeftMemUserOutStrobe_n,
LeftMemUserOutWriteSel_n, RightMemUse
peshell.v
/*
Daniel L. Rosenband
9/28/99
Interface for Annapolis PE
*/
module PEShell (/*AUTOARG*/
// Outputs
Pad_MClk2PE, Pad_MClk2CBCtrl, Pad_MClk2LeftMem, Pad_MClk2RightMem,
Pad_
xmem.v
/*
Daniel L. Rosenband
10/4/99
Instruction Memory 4 X 512 X 8
Ext... is interface for outside (LAD bus) to access instruction memory
*/
module XMEM (/*AUTOARG*/
// Outputs
XDataOut,
regfile.v
/*
Daniel L. Rosenband
9/30/99
*/
module RegFile (/*AUTOARG*/
// Outputs
IRF2ALU, IRF2ALUUnlatched, RaDataOut, RbDataOut,
RaDataOutUnlatched, AEqB, AEq0, ALt0, LinkPCRFOut,
LinkPCAddrR