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dizhi.v
module dizhi(k,,q1,clk,en);
input clk,en;
output [2:0] k;
output [2:0] q1;
reg q0,q9,q2;
reg [2:0] k;
reg [2:0] q;
assign q1={q2,q9,q0}-1;
always @(posedge
counter.v
module counter (clkin,clkin1,countout);
input clkin,clkin1;
output [2:0] countout;
reg [2:0] countout;
always@(posedge clkin1 )
if(!clkin)
begin
if(countout
jiaozhiqi.v
`include"./shuru.v"
`include"./counter.v"
`include"./dizhi.v"
`include"./selecter1.v"
`include"./control.v"
`include"./ram.v"
`include"./jie.v"
module jiaozhiqi(clk,clk1,en,predate,dateout,da
jie.v
module jie(datein,datejie,addr,addrin,clk1,clk);
input datein,clk,clk1;
input [2:0]addr;
input [2:0]addrin;
output datejie;
reg ram [6:0];
assign datejie = (!clk)? ram[add
ram.v
module ram(date,dateout,addr,ena,read,write);
input date;
input [2:0]addr;
input ena;
input read,write;
output dateout;
reg ram [6:0];
assign dateout = (read&&ena)? ra
control.v
module control (addrin,countin,datein,clk,dateout,addrout);
input [2:0] addrin;
input [2:0] countin;
input clk,datein;
output dateout;
output [2:0] addrout;
assign dateout=(!clk)? da
shuru.v
module shuru(q2,clk,en,preout);
input clk,en;
output q2,preout;
reg q0,q1,q2;
assign preout=q2;
always @(posedge clk or posedge en )
if(en)
{q2,q1,q0}
sram.v
/******************************************************************************
* File Name : sram.v *
* Function : 2K*8bit Asynchronous CMOS Static RAM *
adc.v
//-------------------- adc.v ------------------------
module adc (nconvst, nbusy, data);
input nconvst; // A/D 启动脉冲ST，即上图中
output nbusy; // A/D 工作标志，即上图中
output data