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sysid.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
sdram.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
cf.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
sysid.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
sm.v
// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.
/*******************************
* Sample solution: - Synthesizable RTL
* - Separate signals,
and2.v
// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.
`timescale 1 ns / 1 ns
///////////////////////////////////////////////////
// and2 cell:
// W
set.v
// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.
`timescale 1ns/1ns
module cache_set(addr, data, hit, oen, wen);
input addr, oen, wen;
inout
memory.v
// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.
`timescale 1 ns / 1 ns
module memory(clk, addr, data, rw, strb, rdy);
input clk, addr, rw, s
gates.v
// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.
`timescale 1 ns / 1 ns
///////////////////////////////////////////////////
// and2 cell:
// W