regfile.v

麻省理工的一个实验室实现的MIPS IP CORE

/* 
Daniel L. Rosenband
9/30/99
*/

module RegFile (/*AUTOARG*/
   // Outputs
   IRF2ALU, IRF2ALUUnlatched, RaDataOut, RbDataOut, 
   RaDataOutUnlatched, AEqB, AEq0, ALt0, LinkPCRFOut, 
   LinkPCAddrRFOut, 
   // Inputs
   Clk, ClkEN, RwDataIn, RwAddrIn, RwENIn, IIF2RF, IIF2RFUnlatched, 
   LinkPC, PCP8, LinkPCAddr, ALUResultUnlatched, 
   ALUResultRegAddrUnlatched, MemResultUnlatched, 
   MemResultRegAddrUnlatched
   );

   output [31:0] IRF2ALU;
   output [31:0] IRF2ALUUnlatched;

   output [31:0] RaDataOut;	// data output for read port A
   output [31:0] RbDataOut;	// data output for read port B
   output [31:0] RaDataOutUnlatched;  // used for JR
   
   output 	 AEqB;
   output 	 AEq0;
   output 	 ALt0;

   output 	 LinkPCRFOut;	// PCP8 is in RbDataOut.  (rb because ra is used for jalr)
   output [4:0]  LinkPCAddrRFOut;
   
   input 	 Clk;
   input 	 ClkEN;			// no state is modified if clock is not enabled
      
   input [31:0]  RwDataIn;		// data input for write port
   input [4:0] 	 RwAddrIn;		// addr for write port
   input 	 RwENIn;		// enable writing

   input [31:0]  IIF2RF;
   input [31:0]  IIF2RFUnlatched;

   input 	 LinkPC;	// from IF stage
   input [31:0]	 PCP8;		
   input [4:0] 	 LinkPCAddr;
   
   input [31:0]  ALUResultUnlatched;// for bypass
   input [4:0] 	 ALUResultRegAddrUnlatched;
   input [31:0]  MemResultUnlatched;
   input [4:0] 	 MemResultRegAddrUnlatched;

   reg [31:0] 	 IRF2ALU;
   
   wire [4:0] 	 raAddrIn;	// address for read port A
   wire [4:0] 	 rbAddrIn;		// address for read port B

   reg [31:0] 	 RaDataOut;
   reg [31:0] 	 RbDataOut;
   reg [31:0] 	 newRaDataOut;
   reg [31:0] 	 newRbDataOut;
   
   reg 		 AEqB;
   reg 		 AEq0;
   reg 		 ALt0;

   reg 		 LinkPCRFOut;
   reg [4:0] 	 LinkPCAddrRFOut;

   wire [31:0] 	 rwData;
   reg [4:0] 	 raAddr0;
   reg [4:0] 	 raAddr1;
   reg [4:0] 	 rbAddr0;
   reg [4:0] 	 rbAddr1;

//   wire [31:0] 	 raData;
//   wire [31:0] 	 rbData;
   reg [31:0] 	 raData;
   reg [31:0] 	 rbData;
   
   wire 	 writeEnable_a;
   wire 	 writeEnable_b;
   wire [4:0] 	 writeAddress;
   wire [31:0] 	 dummyWire;

   reg [31:0] regs [0:31];

// renaming
   assign 	 RaDataOutUnlatched = newRaDataOut;
   assign 	 raAddrIn = IIF2RFUnlatched[25:21];
   assign 	 rbAddrIn = IIF2RFUnlatched[20:16];
   
   assign 	 IRF2ALUUnlatched = IIF2RF;

   always @ (posedge Clk)
     if (ClkEN)
       IRF2ALU = IRF2ALUUnlatched;

   always @ (posedge Clk)
     if (ClkEN)
       begin
	  RaDataOut <= newRaDataOut;
	  RbDataOut <= newRbDataOut;
	  raAddr0 <= raAddrIn;
	  raAddr1 <= raAddrIn;
	  rbAddr0 <= rbAddrIn;
	  rbAddr1 <= rbAddrIn;
       end // if (ClkEN)
   
   always @ (/*AUTOSENSE*/ALUResultRegAddrUnlatched
	     or ALUResultUnlatched or LinkPC
	     or MemResultRegAddrUnlatched or MemResultUnlatched
	     or PCP8 or raAddr0 or raData or rbAddr0 or rbData
	     or rwData or writeAddress)
     begin
	if (raAddr0 == 5'b0)
	  newRaDataOut = 32'b0;
	if (raAddr0 == ALUResultRegAddrUnlatched)
	  newRaDataOut = ALUResultUnlatched;
	else
	  if (raAddr0 == MemResultRegAddrUnlatched)
	    newRaDataOut = MemResultUnlatched;
	  else
	    if (raAddr0 == writeAddress)
	      newRaDataOut = rwData;
	    else
	      newRaDataOut = raData;

	if (LinkPC)
	  newRbDataOut = PCP8;
	else
	  if (rbAddr0 == 5'b0)
	    newRbDataOut = 32'b0;
	  else
	    if (rbAddr0 == ALUResultRegAddrUnlatched)
	      newRbDataOut = ALUResultUnlatched;
	    else
	      if (rbAddr0 == MemResultRegAddrUnlatched)
		newRbDataOut = MemResultUnlatched;
	      else
		if (rbAddr0 == writeAddress)
		  newRbDataOut = rwData;
		else
		  newRbDataOut = rbData;
     end

   always @ (/*AUTOSENSE*/newRaDataOut or newRbDataOut)
     begin
	AEqB = (newRaDataOut == newRbDataOut);
	AEq0 = (newRaDataOut == 0);
	ALt0 = (newRaDataOut[31]);
     end // always @ (posedge Clk)
      
   assign 	 writeEnable_a = (RwENIn && ClkEN);
   assign 	 writeEnable_b = (RwENIn && ClkEN);
   assign 	 writeAddress = (RwAddrIn);
   assign 	 rwData = RwDataIn;

   always @ (posedge Clk)
     if (ClkEN)
       begin
	  LinkPCRFOut <= LinkPC;
	  LinkPCAddrRFOut <= LinkPCAddr;
       end // if (ClkEN)





   always @ (negedge Clk)
     if (ClkEN)
       begin
         if (writeEnable_a)
            regs[writeAddress] <= rwData;
         raData <= regs[raAddr0];
         rbData <= regs[rbAddr0];
       end // if (ClkEN)
       








/*

   RAM32X32D RAM32X32D_A (
			  // Outputs
			  .RData	(raData[31:0]),
//			  .WpData	(rdiagData[31:0]),
			  // Inputs
			  .Clk		(Clk),
			  .WData	(rwData[31:0]),
			  .WAddr	(writeAddress[4:0]),
			  .WEN		(writeEnable_a),
			  .RAddr0	(raAddr0[4:0]),
			  .RAddr1	(raAddr1[4:0]));

   RAM32X32D RAM32X32D_B (
			  // Outputs
			  .RData	(rbData[31:0]),
			  .WpData       (dummyWire),
			  // Inputs
			  .Clk		(Clk),
			  .WData	(rwData[31:0]),
			  .WAddr	(writeAddress[4:0]),
			  .WEN		(writeEnable_b),
			  .RAddr0	(rbAddr0[4:0]),
			  .RAddr1	(rbAddr1[4:0]));

*/

endmodule // RegFile