memstage.v

麻省理工的一个实验室实现的MIPS IP CORE

/*
 Daniel L. Rosenband
 10/12/99
 
 ALU
 
*/

module MemStage (/*AUTOARG*/
   // Outputs
   DMemAddr, DMemWE, DMemWriteData, MemResult, MemResultRegAddr, 
   MemResultUnlatched, MemResultRegAddrUnlatched, MemResultValid, 
   // Inputs
   Clk, ClkEN, IALU2MEM, ALUResult, ALUResultRegAddr, ALURtDataOut, 
   DMemDataIn
   );

   output [8:0] DMemAddr;
   output 	DMemWE;
   output [31:0] DMemWriteData;

   output [31:0] MemResult;
   output [4:0]  MemResultRegAddr;
   output [31:0] MemResultUnlatched;
   output [4:0]  MemResultRegAddrUnlatched;
   output 	 MemResultValid;
   
   input 	 Clk;
   input 	 ClkEN;
   input [31:0]	 IALU2MEM;
   input [31:0]  ALUResult;
   input [4:0] 	 ALUResultRegAddr;
   input [31:0]  ALURtDataOut;
   input [31:0]  DMemDataIn;

   reg [31:0] 	 MemResult;
   reg [4:0] 	 MemResultRegAddr;
   reg [31:0] 	 newMemResult;
   wire [4:0] 	 newMemResultRegAddr;

   wire [31:0] 	 MemResultUnlatched;
   wire [4:0] 	 MemResultRegAddrUnlatched;
   reg 		 MemResultValid;   
   
   wire [31:0] 	 i;
   wire [5:0]  op;

   wire        iIsLW;
   wire        iIsSW;
   
// rename signals
   assign      MemResultUnlatched = newMemResult;
   assign      MemResultRegAddrUnlatched = newMemResultRegAddr;

   assign      i = IALU2MEM;
   assign      op = i[31:26];

   assign      iIsSW = (op == 6'b101011);
   assign      iIsLW = (op == 6'b100011);

   assign      DMemAddr = ALUResult[10:2];
   assign      DMemWE = iIsSW;
   assign      DMemWriteData = ALURtDataOut;
   
   always @ (posedge Clk)
     if (ClkEN)
       begin
	  MemResult <= newMemResult;
	  MemResultRegAddr <= newMemResultRegAddr;
       end // if (ClkEN)

   always @ (/*AUTOSENSE*/ALUResult or DMemDataIn or iIsLW)
     begin
	if (iIsLW)
	  newMemResult = DMemDataIn;
	else
	  newMemResult = ALUResult;
     end

   assign newMemResultRegAddr = ALUResultRegAddr;

   always @ (posedge Clk)
     MemResultValid <= (!iIsSW);
   
endmodule // MemStage