danram16x1d.v

来自「麻省理工的一个实验室实现的MIPS IP CORE」· Verilog 代码 · 共 45 行

module DanRAM16X1D (/*AUTOARG*/
   // Outputs
  DPO, 
   // Inputs
   WE, WCLK, DPRA3, DPRA2, DPRA1, DPRA0, D, A3, A2, A1, A0
   );

   /*AUTOINPUT*/
   // Beginning of automatic inputs (from unused autoinst inputs)
   input		A0;			// To RAM16X1D of RAM16X1D.v
   input		A1;			// To RAM16X1D of RAM16X1D.v
   input		A2;			// To RAM16X1D of RAM16X1D.v
   input		A3;			// To RAM16X1D of RAM16X1D.v
   input		D;			// To RAM16X1D of RAM16X1D.v
   input		DPRA0;			// To RAM16X1D of RAM16X1D.v
   input		DPRA1;			// To RAM16X1D of RAM16X1D.v
   input		DPRA2;			// To RAM16X1D of RAM16X1D.v
   input		DPRA3;			// To RAM16X1D of RAM16X1D.v
   input		WCLK;			// To RAM16X1D of RAM16X1D.v
   input		WE;			// To RAM16X1D of RAM16X1D.v
   // End of automatics

   /*AUTOOUTPUT*/
   // Beginning of automatic outputs (from unused autoinst outputs)
   output		DPO;			// From RAM16X1D of RAM16X1D.v
   // End of automatics

   RAM16X1D RAM16X1D (/*AUTOINST*/
		      // Outputs
		      .DPO		(DPO),
		      // Inputs
		      .A0		(A0),
		      .A1		(A1),
		      .A2		(A2),
		      .A3		(A3),
		      .D		(D),
		      .DPRA0		(DPRA0),
		      .DPRA1		(DPRA1),
		      .DPRA2		(DPRA2),
		      .DPRA3		(DPRA3),
		      .WCLK		(WCLK),
		      .WE		(WE));

endmodule // DanRAM16X1D