pemips.v

麻省理工的一个实验室实现的MIPS IP CORE

/*
 Daniel L. Rosenband
 9/28/99
 
 Empty PE
 
*/

module PEMIPS (/*AUTOARG*/
   // Outputs
   LeftMemUserOutData, LeftMemUserOutAddr, LeftMemUserOutStrobe_n, 
   LeftMemUserOutWriteSel_n, RightMemUserOutData, 
   RightMemUserOutAddr, RightMemUserOutStrobe_n, 
   RightMemUserOutWriteSel_n, LADUserOutData, LADUserOutAckStrobe_n, 
   LADUserOutIntReq_n, 
   // Inputs
   KClk, MClk, MClk180, Reset, LeftMemUserInData, 
   LeftMemUserInDataValid_n, RightMemUserInData, 
   RightMemUserInDataValid_n, LADUserInAddr, LADUserInData, 
   LADUserInRegStrobe_n, LADUserInMemStrobe_n, LADUserInWriteSel_n
   );
   
// signals to/from left mem   
   output [31:0] LeftMemUserOutData;
   output [18:0] LeftMemUserOutAddr;
   output 	 LeftMemUserOutStrobe_n;
   output 	 LeftMemUserOutWriteSel_n;

// signals to/from right mem   
   output [31:0] RightMemUserOutData;
   output [18:0] RightMemUserOutAddr;
   output 	 RightMemUserOutStrobe_n;
   output 	 RightMemUserOutWriteSel_n;

// signals to/from lad interface
   output [31:0] LADUserOutData;
   output        LADUserOutAckStrobe_n;
   output        LADUserOutIntReq_n;

   input 	 KClk;
   input 	 MClk;
   input 	 MClk180;
   input 	 Reset;
      
// signals to/from left mem   
   input [31:0]  LeftMemUserInData;
   input 	 LeftMemUserInDataValid_n;

// signals to/from right mem   
   input [31:0]  RightMemUserInData;
   input 	 RightMemUserInDataValid_n;

// signals to/from lad interface
   input [21:0]  LADUserInAddr;
   input [31:0]  LADUserInData;
   input 	 LADUserInRegStrobe_n;
   input 	 LADUserInMemStrobe_n;
   input 	 LADUserInWriteSel_n;

   wire 	 writeIMEM;
   wire 	 writeDMEM;
   wire [31:0] 	 imemDataOut;
   wire [31:0] 	 dmemDataOut;

   reg 		 readIMEM;

// if outputs
   wire [31:0] 	 instrAddr;
   wire [31:0] 	 iIF2RF;
   wire [31:0] 	 iIF2RFUnlatched;
   wire 	 linkPC;	// link instruction (pc should be stored...)
   wire [31:0] 	 pcP8;		// pc + 8 (for link instruction)
   wire [4:0] 	 linkPCAddr;
// if inputs   
   wire 	 ifClkEN;

// regfile outputs
   wire [31:0] 	 iRF2ALU;
   wire [31:0] 	 iRF2ALUUnlatched;
   wire [31:0]	 raDataOut;
   wire [31:0] 	 rbDataOut;
   wire [31:0]	 raDataOutUnlatched;
   wire 	 aEqB;
   wire 	 aEq0;
   wire 	 aLt0;
   wire 	 linkPCRFOut;
   wire [4:0] 	 linkPCAddrRFOut;
// regfile inputs
   wire 	 regClkEN;

// ALU outputs
   wire [31:0] 	 iALU2MEM;
   wire [31:0] 	 aluResult;
   wire [4:0] 	 aluResultRegAddr;
   wire [31:0] 	 aluResultUnlatched;
   wire [4:0] 	 aluResultRegAddrUnlatched;
   wire [31:0] 	 aluRtDataOut;
// ALU inputs
   wire 	 aluClkEN;

// MemStage outputs
   wire [8:0] 	 dMemAddr;
   wire 	 dMemWE;
   wire [31:0]	 dMemWriteData;
   wire [31:0]	 memResult;
   wire [4:0] 	 memResultRegAddr;
   wire [31:0] 	 memResultUnlatched;
   wire [4:0] 	 memResultRegAddrUnlatched;
   wire 	 memResultValid;
// MemStage inputs
   wire 	 memStageClkEN;
   
// IMEM outputs
   wire [31:0] 	 instr;

// DMEM outputs
   wire [31:0] 	 dMemDataIn;	// data out of data memory into memstage

   reg 		 newProgKClk;	// when set we are loading a new program -- pc does nothing
   reg 		 newProgMClk;
   
   // signals to/from left mem   
   assign 	 LeftMemUserOutData = 32'b0;
   assign 	 LeftMemUserOutAddr = 19'b0;
   assign 	 LeftMemUserOutStrobe_n = 1'b1;
   assign 	 LeftMemUserOutWriteSel_n = 1'b1;

// signals to/from right mem   
   assign 	 RightMemUserOutData = 32'b0;
   assign 	 RightMemUserOutAddr = 19'b0;
   assign 	 RightMemUserOutStrobe_n = 1'b1;
   assign 	 RightMemUserOutWriteSel_n = 1'b1;

// signals to/from lad interface
   assign 	 LADUserOutData = readIMEM  ? imemDataOut : dmemDataOut;
   assign 	 LADUserOutAckStrobe_n = 1'b1;
   assign 	 LADUserOutIntReq_n = 1'b1;

   always @ (posedge KClk)
     readIMEM <= LADUserInAddr[11];

   always @ (posedge KClk or posedge Reset)
     if (Reset)
       newProgKClk <= 1'b1;
     else
       if (((!LADUserInRegStrobe_n) && (!LADUserInWriteSel_n)) && (LADUserInAddr[14:2] == 13'h0004))
	 newProgKClk <= 1'b1;
       else
	 if (((!LADUserInRegStrobe_n) && (!LADUserInWriteSel_n)) && (LADUserInAddr[14:2] == 13'h0005))
	   newProgKClk <= 1'b0;

   always @ (posedge MClk or posedge Reset)
     if (Reset)
       newProgMClk <= 1'b1;
     else
       newProgMClk <= newProgKClk;
   
   assign 	 writeIMEM = ((!LADUserInRegStrobe_n) && (!LADUserInWriteSel_n)) &&
		 (LADUserInAddr[14:11] == 4'b0111);
   assign 	 writeDMEM = ((!LADUserInRegStrobe_n) && (!LADUserInWriteSel_n)) &&
		 (LADUserInAddr[14:11] == 4'b0110);

   assign 	 ifClkEN = 1'b1;
   assign 	 regClkEN = 1'b1;
   assign 	 aluClkEN = 1'b1;
   assign 	 memStageClkEN = 1'b1;
   
   IF IF (
	  // Outputs
	  .IAddr			(instrAddr[31:0]),        
	  .IIF2RF		        (iIF2RF),
	  .IIF2RFUnlatched	        (iIF2RFUnlatched),
	  .LinkPC	                (linkPC),
	  .PCP8                         (pcP8),
	  .LinkPCAddr                   (linkPCAddr),
	  // Inputs
	  .MClk				(MClk),
	  .IFClkEN			(ifClkEN),
	  .NewProg                      (newProgMClk),
	  .IIn				(instr[31:0]),
	  .AEqB				(aEqB),
	  .AEq0				(aEq0),
	  .ALt0				(aLt0),
	  .RaData			(raDataOutUnlatched[31:0]));

   RegFile RegFile (
		    // Outputs
		    .IRF2ALU            (iRF2ALU[31:0]),
		    .IRF2ALUUnlatched   (iRF2ALUUnlatched[31:0]),
		    .RaDataOut		(raDataOut[31:0]),
		    .RbDataOut		(rbDataOut[31:0]),
		    .RaDataOutUnlatched (raDataOutUnlatched[31:0]),
		    .AEqB		(aEqB),
		    .AEq0		(aEq0),
		    .ALt0		(aLt0),
		    .LinkPCRFOut        (linkPCRFOut),
		    .LinkPCAddrRFOut    (linkPCAddrRFOut),
		    // Inputs
		    .Clk		(MClk),
		    .ClkEN		(regClkEN),
		    .RwDataIn		(memResult),
		    .RwAddrIn		(memResultRegAddr),
		    .RwENIn		(memResultValid),
		    .IIF2RF	        (iIF2RF[31:0]),
		    .IIF2RFUnlatched    (iIF2RFUnlatched[31:0]),
		    .LinkPC             (linkPC),
		    .PCP8               (pcP8),
		    .LinkPCAddr         (linkPCAddr),
		    .ALUResultUnlatched (aluResultUnlatched[31:0]),
		    .ALUResultRegAddrUnlatched (aluResultRegAddrUnlatched[4:0]),
		    .MemResultUnlatched (memResultUnlatched[31:0]),
		    .MemResultRegAddrUnlatched (memResultRegAddrUnlatched[4:0]));

   ALU ALU (
	    // Outputs
	    .IALU2MEM                   (iALU2MEM[31:0]),
	    .ALUResult			(aluResult[31:0]),
	    .ALUResultRegAddr		(aluResultRegAddr[4:0]),
	    .ALUResultUnlatched		(aluResultUnlatched[31:0]),
	    .ALUResultRegAddrUnlatched	(aluResultRegAddrUnlatched[4:0]),
	    .ALURtDataOut               (aluRtDataOut[31:0]),
	    // Inputs
	    .Clk			(MClk),
	    .ClkEN			(aluClkEN),
	    .IRF2ALU			(iRF2ALU[31:0]),
	    .IRF2ALUUnlatched		(iRF2ALUUnlatched[31:0]),
	    .RsData			(raDataOut[31:0]),
	    .RtData			(rbDataOut[31:0]),
	    .LinkPCRFOut		(linkPCRFOut),
	    .LinkPCAddrRFOut		(linkPCAddrRFOut[4:0]));

   MemStage MemStage (
		      // Outputs
		      .DMemAddr		(dMemAddr[8:0]),
		      .DMemWE		(dMemWE),
		      .DMemWriteData	(dMemWriteData[31:0]),
		      .MemResult	(memResult[31:0]),
		      .MemResultRegAddr	(memResultRegAddr[4:0]),
		      .MemResultUnlatched(memResultUnlatched[31:0]),
		      .MemResultRegAddrUnlatched(memResultRegAddrUnlatched[4:0]),
		      .MemResultValid   (memResultValid),
		      // Inputs
		      .Clk		(MClk),
		      .ClkEN		(memStageClkEN),
		      .IALU2MEM		(iALU2MEM[31:0]),
		      .ALUResult	(aluResult[31:0]),
		      .ALUResultRegAddr	(aluResultRegAddr[4:0]),
		      .ALURtDataOut	(aluRtDataOut[31:0]),
		      .DMemDataIn	(dMemDataIn[31:0]));
   
   XMEM IMEM (
	      // Outputs
	      .XDataOut			(instr[31:0]),
	      .ExtDataOut		(imemDataOut[31:0]),
	      // Inputs
	      .MClk180			(MClk180),
	      .KClk			(KClk),
	      .Reset			(Reset),
	      .XAddr    		(instrAddr[10:2]),
	      .XEnable		        (1'b1),
	      .XWE                      (1'b0),
	      .XDataIn		        (32'bx),
	      .ExtAddr			(LADUserInAddr[10:2]),
	      .ExtDataIn		(LADUserInData[31:0]),
	      .ExtEnable		(1'b1),
	      .ExtWE			(writeIMEM));	  

   XMEM DMEM (
	      // Outputs
	      .XDataOut			(dMemDataIn[31:0]),
	      .ExtDataOut		(dmemDataOut[31:0]),
	      // Inputs
	      .MClk180			(MClk180),
	      .KClk			(KClk),
	      .Reset			(Reset),
	      .XAddr    		(dMemAddr[8:0]),
	      .XEnable		        (1'b1),
	      .XWE                      (dMemWE),
	      .XDataIn                  (dMemWriteData[31:0]),
	      .ExtAddr			(LADUserInAddr[10:2]),
	      .ExtDataIn		(LADUserInData[31:0]),
	      .ExtEnable		(1'b1),
	      .ExtWE			(writeDMEM));	  
   
   
endmodule // PEEmpty