peshell.v

麻省理工的一个实验室实现的MIPS IP CORE

/*
 Daniel L. Rosenband
 9/28/99
 
 Interface for Annapolis PE
 
*/

module PEShell (/*AUTOARG*/
   // Outputs
   Pad_MClk2PE, Pad_MClk2CBCtrl, Pad_MClk2LeftMem, Pad_MClk2RightMem, 
   Pad_PClk2PE, Pad_PClk2CBCtrl, Pad_Audio, Pad_LADBus_Ack_n, 
   Pad_LADBus_IntReq_n, Pad_LADBus_DMA0DataOK_n, 
   Pad_LADBus_DMA0BurstOK, Pad_LADBus_DMA1DataOK_n, 
   Pad_LADBus_DMA1BurstOK, Pad_LADBus_RegDataOK_n, 
   Pad_LADBus_RegBurstOK, Pad_LADBus_ForceKClk_n, Pad_LeftMemAddr, 
   Pad_LeftMemByteWR_n, Pad_LeftMemCS_n, Pad_LeftMemCE_n, 
   Pad_LeftMemWE_n, Pad_LeftMemOE_n, Pad_LeftMemSleepEN, 
   Pad_LeftMemLoadEN_n, Pad_LeftMemBurstMode, Pad_RightMemAddr, 
   Pad_RightMemByteWR_n, Pad_RightMemCS_n, Pad_RightMemCE_n, 
   Pad_RightMemWE_n, Pad_RightMemOE_n, Pad_RightMemSleepEN, 
   Pad_RightMemLoadEN_n, Pad_RightMemFlowThruEN_n, 
   // Inouts
   Pad_LADBus_AddrData, Pad_LeftMemData, Pad_RightMemData, 
   Pad_LeftIO, Pad_RightIO, 
   // Inputs
   Pad_Reset, Pad_FClk, Pad_MClk, Pad_PClk, Pad_KClk, Pad_IOClk, 
   Pad_LADBus_AS_n, Pad_LADBus_DS_n, Pad_LADBus_Reg_n, 
   Pad_LADBus_WR_n, Pad_LADBus_CS_n
   );

   inout [31:0] Pad_LADBus_AddrData;
   inout [35:0] Pad_LeftMemData;
   inout [35:0] Pad_RightMemData;

   inout [12:0]	Pad_LeftIO;
   inout [12:0]	Pad_RightIO;
   
   output Pad_MClk2PE;
   output Pad_MClk2CBCtrl;
   output Pad_MClk2LeftMem;
   output Pad_MClk2RightMem;
   output Pad_PClk2PE;
   output Pad_PClk2CBCtrl;

   output Pad_Audio;
   
   output  Pad_LADBus_Ack_n;
   output  Pad_LADBus_IntReq_n;
   output  Pad_LADBus_DMA0DataOK_n;
   output  Pad_LADBus_DMA0BurstOK;
   output  Pad_LADBus_DMA1DataOK_n;
   output  Pad_LADBus_DMA1BurstOK;
   output  Pad_LADBus_RegDataOK_n;
   output  Pad_LADBus_RegBurstOK;
   output  Pad_LADBus_ForceKClk_n;
   
   output [18:0] Pad_LeftMemAddr;
   output [3:0]  Pad_LeftMemByteWR_n;
   output 	 Pad_LeftMemCS_n;
   output 	 Pad_LeftMemCE_n;	
   output 	 Pad_LeftMemWE_n;
   output 	 Pad_LeftMemOE_n;
   output 	 Pad_LeftMemSleepEN;
   output 	 Pad_LeftMemLoadEN_n;
   output 	 Pad_LeftMemBurstMode;

   output [18:0] Pad_RightMemAddr;
   output [3:0]  Pad_RightMemByteWR_n;
   output 	 Pad_RightMemCS_n;
   output 	 Pad_RightMemCE_n;	
   output 	 Pad_RightMemWE_n;
   output 	 Pad_RightMemOE_n;
   output 	 Pad_RightMemSleepEN;
   output 	 Pad_RightMemLoadEN_n;
   output 	 Pad_RightMemFlowThruEN_n;
   
   input  Pad_Reset;
   
   input Pad_FClk;
   input Pad_MClk;
   input Pad_PClk;
   input Pad_KClk;
   input Pad_IOClk;
   
   input Pad_LADBus_AS_n;
   input Pad_LADBus_DS_n;
   input Pad_LADBus_Reg_n;
   input Pad_LADBus_WR_n;
   input Pad_LADBus_CS_n;

// signals to/from clock interface   
   wire  kClk; 			// cardbus clk
   wire  pClk;			// one half of MClk (but synchronous?)
   wire  mClk;			// "fast" System clock
   wire  mClk180;			// "fast" System clock

// signals to/from left mem   
   wire [31:0] leftMemUserInData;
   wire        leftMemUserInDataValid_n;
   wire [31:0] leftMemUserOutData;
   wire [18:0] leftMemUserOutAddr;
   wire        leftMemUserOutStrobe_n;
   wire        leftMemUserOutWriteSel_n;

// signals to/from right mem   
   wire [31:0] rightMemUserInData;
   wire        rightMemUserInDataValid_n;
   wire [31:0] rightMemUserOutData;
   wire [18:0] rightMemUserOutAddr;
   wire        rightMemUserOutStrobe_n;
   wire        rightMemUserOutWriteSel_n;

// signals to/from lad interface
   wire [21:0] ladUserInAddr;
   wire [31:0] ladUserInData;
   wire        ladUserInRegStrobe_n;
   wire        ladUserInMemStrobe_n;
   wire        ladUserInWriteSel_n;
   wire [31:0] ladUserOutData;
   wire        ladUserOutAckStrobe_n;
   wire        ladUserOutIntReq_n;

// Misc signals
   wire        reset;

   assign      reset = 1'b0;	// since there is a global reset on start up
      
   PEMIPS PEMIPS (
		    // Outputs
		    .LeftMemUserOutData	       (leftMemUserOutData[31:0]),
		    .LeftMemUserOutAddr	       (leftMemUserOutAddr[18:0]),
		    .LeftMemUserOutStrobe_n    (leftMemUserOutStrobe_n),
		    .LeftMemUserOutWriteSel_n  (leftMemUserOutWriteSel_n),
		    .RightMemUserOutData       (rightMemUserOutData[31:0]),
		    .RightMemUserOutAddr       (rightMemUserOutAddr[18:0]),
		    .RightMemUserOutStrobe_n   (rightMemUserOutStrobe_n),
		    .RightMemUserOutWriteSel_n (rightMemUserOutWriteSel_n),
		    .LADUserOutData	       (ladUserOutData[31:0]),
		    .LADUserOutAckStrobe_n     (ladUserOutAckStrobe_n),
		    .LADUserOutIntReq_n	       (ladUserOutIntReq_n),
		    // Inputs
		    .KClk	               (kClk),
		    .MClk                      (mClk),
		    .MClk180                   (mClk180),
   		    .Reset	               (reset),
		    .LeftMemUserInData	       (leftMemUserInData[31:0]),
		    .LeftMemUserInDataValid_n  (leftMemUserInDataValid_n),
		    .RightMemUserInData	       (rightMemUserInData[31:0]),
		    .RightMemUserInDataValid_n (rightMemUserInDataValid_n),
		    .LADUserInAddr	       (ladUserInAddr[21:0]),
		    .LADUserInData	       (ladUserInData[31:0]),
		    .LADUserInRegStrobe_n      (ladUserInRegStrobe_n),
		    .LADUserInMemStrobe_n      (ladUserInMemStrobe_n),
		    .LADUserInWriteSel_n       (ladUserInWriteSel_n));
   
   AudioIO AudioIO (
		    // Outputs
		    .Pad_Audio		(Pad_Audio));		    // Inputs

      
   ClockIO ClockIO (
		    // Outputs
		    .Pad_MClk2PE	(Pad_MClk2PE),
		    .Pad_MClk2CBCtrl	(Pad_MClk2CBCtrl),
		    .Pad_MClk2LeftMem	(Pad_MClk2LeftMem),
		    .Pad_MClk2RightMem  (Pad_MClk2RightMem),
		    .Pad_PClk2PE	(Pad_PClk2PE),
		    .Pad_PClk2CBCtrl	(Pad_PClk2CBCtrl),
		    .KClk		(kClk),
		    .PClk		(pClk),
		    .MClk		(mClk),
		    .MClk180		(mClk180),
		    // Inputs
		    .Reset		(reset),
		    .Pad_FClk		(Pad_FClk),
		    .Pad_MClk		(Pad_MClk),
		    .Pad_PClk		(Pad_PClk),
		    .Pad_KClk		(Pad_KClk),
		    .Pad_IOClk		(Pad_IOClk));

   IOConn IOConn (
		  // Outputs
		  // Inouts
		  .LeftIO		(Pad_LeftIO[12:0]),
		  .RightIO		(Pad_RightIO[12:0]));		  // Inputs


   ResetIO ResetIO (
		    // Outputs
		    // Inputs
		    .Pad_ResetIn	(Pad_Reset),
		    .Clk		(kClk));

   MemIO LeftMemIO (
		// Outputs
		.Pad_MemAddr		(Pad_LeftMemAddr[18:0]),
		.Pad_ByteWR_n		(Pad_LeftMemByteWR_n[3:0]),
		.Pad_CS_n		(Pad_LeftMemCS_n),
		.Pad_CE_n		(Pad_LeftMemCE_n),
		.Pad_WE_n		(Pad_LeftMemWE_n),
		.Pad_OE_n		(Pad_LeftMemOE_n),
		.Pad_LoadEN_n		(Pad_LeftMemLoadEN_n),
		.Pad_SleepEN		(Pad_LeftMemSleepEN),
		.Pad_BurstMode		(Pad_LeftMemBurstMode),
		.UserInData		(leftMemUserInData[31:0]),
		.UserInDataValid_n	(leftMemUserInDataValid_n),
		// Inouts
		.Pad_MemData		(Pad_LeftMemData[35:0]),
		// Inputs
		.MClk			(mClk),
		.Reset			(reset),
		.UserOutData		(leftMemUserOutData[31:0]),
		.UserOutAddr		(leftMemUserOutAddr[18:0]),
		.UserOutStrobe_n	(leftMemUserOutStrobe_n),
		.UserOutWriteSel_n	(leftMemUserOutWriteSel_n));

   MemIO RightMemIO (
		// Outputs
		.Pad_MemAddr		(Pad_RightMemAddr[18:0]),
		.Pad_ByteWR_n		(Pad_RightMemByteWR_n[3:0]),
		.Pad_CS_n		(Pad_RightMemCS_n),
		.Pad_CE_n		(Pad_RightMemCE_n),
		.Pad_WE_n		(Pad_RightMemWE_n),
		.Pad_OE_n		(Pad_RightMemOE_n),
		.Pad_LoadEN_n		(Pad_RightMemLoadEN_n),
		.Pad_SleepEN		(Pad_RightMemSleepEN),
		.Pad_BurstMode		(Pad_RightMemFlowThruEN_n),
		.UserInData		(rightMemUserInData[31:0]),
		.UserInDataValid_n	(rightMemUserInDataValid_n),
		// Inouts
		.Pad_MemData		(Pad_RightMemData[35:0]),
		// Inputs
		.MClk			(mClk),
		.Reset			(reset),
		.UserOutData		(rightMemUserOutData[31:0]),
		.UserOutAddr		(rightMemUserOutAddr[18:0]),
		.UserOutStrobe_n	(rightMemUserOutStrobe_n),
		.UserOutWriteSel_n	(rightMemUserOutWriteSel_n));

   LADBus LADBus (
		  // Outputs
		  .Pad_LADBus_Ack_n	       (Pad_LADBus_Ack_n),
		  .Pad_LADBus_IntReq_n	       (Pad_LADBus_IntReq_n),
		  .Pad_LADBus_DMA0DataOK_n     (Pad_LADBus_DMA0DataOK_n),
		  .Pad_LADBus_DMA0BurstOK      (Pad_LADBus_DMA0BurstOK),
		  .Pad_LADBus_DMA1DataOK_n     (Pad_LADBus_DMA1DataOK_n),
		  .Pad_LADBus_DMA1BurstOK      (Pad_LADBus_DMA1BurstOK),
		  .Pad_LADBus_RegDataOK_n      (Pad_LADBus_RegDataOK_n),
		  .Pad_LADBus_RegBurstOK       (Pad_LADBus_RegBurstOK),
		  .Pad_LADBus_ForceKClk_n      (Pad_LADBus_ForceKClk_n),
		  .UserInAddr		       (ladUserInAddr[21:0]),
		  .UserInData		       (ladUserInData[31:0]),
		  .UserInRegStrobe_n	       (ladUserInRegStrobe_n),
		  .UserInMemStrobe_n	       (ladUserInMemStrobe_n),
		  .UserInWriteSel_n	       (ladUserInWriteSel_n),
		  // Inouts
		  .Pad_LADBus_AddrData	(Pad_LADBus_AddrData[31:0]),
		  // Inputs
		  .KClk			(kClk),
		  .Reset		(reset),
		  .Pad_LADBus_AS_n	(Pad_LADBus_AS_n),
		  .Pad_LADBus_DS_n	(Pad_LADBus_DS_n),
		  .Pad_LADBus_Reg_n	(Pad_LADBus_Reg_n),
		  .Pad_LADBus_WR_n	(Pad_LADBus_WR_n),
		  .Pad_LADBus_CS_n	(Pad_LADBus_CS_n),
		  .UserOutData		(ladUserOutData[31:0]),
		  .UserOutAckStrobe_n	(ladUserOutAckStrobe_n),
		  .UserOutIntReq_n	(ladUserOutIntReq_n));
   
      
endmodule // PEPackage