xmem.v

麻省理工的一个实验室实现的MIPS IP CORE

/*
 Daniel L. Rosenband
 10/4/99
 
 Instruction Memory  4 X 512 X 8
 
 Ext... is interface for outside (LAD bus) to access instruction memory
 
*/

module XMEM (/*AUTOARG*/
   // Outputs
   XDataOut, ExtDataOut, 
   // Inputs
   MClk180, KClk, Reset, XAddr, XEnable, XWE, XDataIn, ExtAddr, 
   ExtDataIn, ExtEnable, ExtWE
   );

   output [31:0] XDataOut;
   output [31:0] ExtDataOut;
   
   input 	 MClk180;
   input 	 KClk;
   input 	 Reset;

   input [8:0] 	 XAddr;
   input 	 XEnable;
   input 	 XWE;
   input [31:0]  XDataIn;
   input [8:0] 	 ExtAddr;
   input [31:0]	 ExtDataIn;
   input 	 ExtEnable;
   input 	 ExtWE;

   reg [31:0] mem [0:511];
   	 
   reg [31:0] XDataOut;
   reg [31:0] ExtDataOut;


   always @ (posedge MClk180)
     if (XEnable)
       begin
         if (XWE)
            mem[XAddr] = XDataIn;
         XDataOut = mem[XAddr];
/*
         $display("XAddr = 0x%x.", XAddr);
         $display("XDataIn = 0x%x.", XDataIn);
         $display("XDataOut = 0x%x.", XDataOut);
         $display("XWE = 0x%x.", XWE);
*/
       end // if (XEnable)
       
   always @ (posedge MClk180)
     if (ExtEnable)
       begin
         if (ExtWE)
            mem[ExtAddr] = ExtDataIn;
         ExtDataOut = mem[ExtAddr];
/*
         $display("ExtAddr = 0x%x.", ExtAddr);
         $display("ExtDataIn = 0x%x.", ExtDataIn);
         $display("ExtDataOut = 0x%x.", ExtDataOut);
         $display("mem[ExtAddr] = 0x%x.", mem[ExtAddr]);
         $display("ExtWE = 0x%x.", ExtWE);
*/
       end // if (ExtEnable)
       




/*

   RAMB4_S8_S8 XMEM_00 (
			// Outputs
			.DOA		(XDataOut[7:0]),
			.DOB		(ExtDataOut[7:0]),
			// Inputs
			.ADDRA		(XAddr[8:0]),
			.DIA		(XDataIn[7:0]),
			.ENA		(XEnable),
			.CLKA		(MClk180),
			.WEA		(XWE),
			.RSTA		(Reset),
			.ADDRB		(ExtAddr[8:0]),
			.DIB		(ExtDataIn[7:0]),
			.ENB		(ExtEnable),
			.CLKB		(KClk),
			.WEB		(ExtWE),
			.RSTB		(Reset));

   RAMB4_S8_S8 XMEM_01 (
			// Outputs
			.DOA		(XDataOut[15:8]),
			.DOB		(ExtDataOut[15:8]),
			// Inputs
			.ADDRA		(XAddr[8:0]),
			.DIA		(XDataIn[15:8]),
			.ENA		(XEnable),
			.CLKA		(MClk180),
			.WEA		(XWE),
			.RSTA		(Reset),
			.ADDRB		(ExtAddr[8:0]),
			.DIB		(ExtDataIn[15:8]),
			.ENB		(ExtEnable),
			.CLKB		(KClk),
			.WEB		(ExtWE),
			.RSTB		(Reset));

   RAMB4_S8_S8 XMEM_02 (
			// Outputs
			.DOA		(XDataOut[23:16]),
			.DOB		(ExtDataOut[23:16]),
			// Inputs
			.ADDRA		(XAddr[8:0]),
			.DIA		(XDataIn[23:16]),
			.ENA		(XEnable),
			.CLKA		(MClk180),
			.WEA		(XWE),
			.RSTA		(Reset),
			.ADDRB		(ExtAddr[8:0]),
			.DIB		(ExtDataIn[23:16]),
			.ENB		(ExtEnable),
			.CLKB		(KClk),
			.WEB		(ExtWE),
			.RSTB		(Reset));

   RAMB4_S8_S8 XMEM_03 (
			// Outputs
			.DOA		(XDataOut[31:24]),
			.DOB		(ExtDataOut[31:24]),
			// Inputs
			.ADDRA		(XAddr[8:0]),
			.DIA		(XDataIn[31:24]),
			.ENA		(XEnable),
			.CLKA		(MClk180),
			.WEA		(XWE),
			.RSTA		(Reset),
			.ADDRB		(ExtAddr[8:0]),
			.DIB		(ExtDataIn[31:24]),
			.ENB		(ExtEnable),
			.CLKB		(KClk),
			.WEB		(ExtWE),
			.RSTB		(Reset));

*/

endmodule // XMEM