代码搜索结果
找到约 10,000 项符合
V 的代码
pc.v
module pc(din, clk,rst, ld, inc, dout);
input [5:0]din;
input clk, ld, inc,rst;
output [5:0] dout;
reg [5:0] dout;
always @(posedge clk)
if(rst)
dout=0;
else if(ld)
dout=din;
else if(in
control.v
module control(din, clk, rst, arload, pcload, pcinc, drload, acload, acinc, irload, alusel, membus, pcbus, drbus, read);
input [1:0] din;
input clk, rst;
output arload, pcload, pcinc, drload, acloa
top.v
//the very simple cpu
//design by zhxj,2005.4
module top;
reg clk, rst;
wire [5:0] addr;
wire [7:0]data;
wire read;
simplecpu mcpu(data, rst, clk, read, addr);
mem mm(addr,read,data);
initi
main.v
module main(clk, rst, en_out, data_out, rst_out ,ce_out, cmd_out);
input clk,rst;
output en_out, rst_out, ce_out, cmd_out;
output [7:0] data_out;
reg en_out, rst_out=1, ce_out, cmd_out ;
reg [7
clk.v
module clk (reset,f40m,f500k);
input f40m,reset;
output f500k;
reg f500k;
reg [31:0] j;
always @(posedge f40m)
if(reset)
begin
f500k
pctofpga.v
`include "Datapath.v"
`include "Controlpath.v"
`include "Chang3to2.v"
module PcToFPGA(
Clk, //Clock
Reset, //Reset State
Control_R_W, //Con_R_W = 1 ==> PC to FPGA,
//Con_R_W = 0
bidirec.v
module bidirec (oe, //oe = 0 ==> bidir to outp, oe = 1 ==> inp to bidir
clk, //Clock
inp, //Data in
outp, //Data out
bidir); // duport
// Port Declaration
input oe;
input
controlpath.v
module ControlPath(
Clk, //Clock
Reset, //Clear Control Path State
Control_R_W, //Control_R_W = 0 ==> FPGA to PC,
//Control_R_W = 1 ==> PC to FPGA,
PC_Check_1, //PC_Check_1 =
memory.v
// megafunction wizard: %LPM_RAM_DQ%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_ram_dq
// ============================================================
// File Name: memory.v
//
coff_a.v
module coff_a(
indata,
sel,
outdata
);
parameter Data_Width = 20;
input [Data_Width-1:0] indata;
input sel;
output [Data_Width-1:0] outdata;
reg [Data_Width-1:0] outdata;
reg [Data_Width-2:0]