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pcrreg.v
`include "div1.v"
module PcrReg( ResetN, CLKM,
PCRn, NxtPCRn, // pcrctrl
SPCR0, SPCR1, SPCR2, SetFNum, IData, SetPCREn, // csm
PCR12, FNUM, TF,DivEn
led.v
module led(sel,seg,rst,clk,wr,cs,rd,cpu_data,addr);
input clk,rst,wr,cs,rd,a;
output [7:0]sel,seg;
inout [15:0]cpu_data;
input [3:0]addr;
reg [7:0]sel,seg;
reg [15:0]set,set1;
reg wr1;
alway
tb.v
/* This test bench simulates an 8x8 keypad by connecting each of the
8 row inputs to each of the 8 column outputs one at a time. There
will be 64 different combinations of these connections which s
glbl.v
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.9.28.1 2003/11/18 20:41:26 wloo Exp $
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
keypadscan.v
/* The following is example code that is described in the associated application note, XAPPxxx.
This code can be implemented in the smallest 32 macrocell CPLD. The application involves an 8x8
keypa
traffic.v
module traffic(clk,en,lampa,lampb,acount,bcount);
output[7:0] acount,bcount;
output[3:0] lampa,lampb; //?????????????
input clk,en;
reg[7:0] numa,numb;
reg tempa,tempb;
reg[2:0] counta,countb;
reg[7
test.v
/******************************************************************************
*
* File Name: TEST.V
* Version: 1.0
* Date: May 13th, 1998
* Model: BUS Functional
*
define.v
/******************************************************************************
*
* File Name: define.v
* Version: 1.14
* Date: Sept 9, 1999
* Description: define global parameter
sdrm.v
/******************************************************************************
*
* File Name: sdrm.v
* Version: 1.14
* Date: Sept 9, 1999
* Description: Top level module
* Depend
receiver.v
module uart2(clk, rst_n, outdate, outbyte);
input clk, rst_n, outdate;
output [7:0] outbyte;
reg [7:0] outbyte, store;
reg [3:0] counter, st, next_st;
reg pre_outbit;
parameter st_0 = 0, st_1 =