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ram_basic.v
module ram_basic (clk, CS, WR, addr, data_in, data_out, en);
input clk;
input CS; //CS = 1, RAM enable
input WR; //WR =1 then WRite enable; WR = 0 then read enable
in
ram_basic.v
module ram_basic (clk, CS, WR, addr, data_in, data_out, en);
input clk;
input CS; //CS = 1, RAM enable
input WR; //WR =1 then WRite enable; WR = 0 then read enable
in
ram_basic_tb.v
`timescale 1ns/10ps
module ram_basic_tb;
reg clk;
reg CS; //CS = 1, RAM enable
reg WR; //WR =1 then WRite enable; WR = 0 then read enable
reg en; //data_out
ram_basic.v
module ram_basic (clk, CS, WR, addr, data_in, data_out, en);
input clk;
input CS; //CS = 1, RAM enable
input WR; //WR =1 then WRite enable; WR = 0 then read enable
in
recon0.v
棖枖搼憪拺拺拺拺憫憫憫憫悙憭敃枛搾搾搾搾摃殱灊洑枙枙枙枙摀摀摀摀棗晹搾悙憭憭憭憭憫憫憫憫悙憭敃枛挀挀挀挀挄櫇灊洐晼晼晼晼摀摀摀摀棖枖搼憪拺拺拺拺憫憫憫憫悙憭敃枛搾搾搾搾憯槣潨殬枙枙枙枙摀摀摀摀棗晹搾悙憭憭憭憭憫憫憫憫彁憮摃枟挀挀挀挀悡棜湜櫁晼晼晼晼摀摀摀摀棖枖搼憪拺拺拺拺憫憫憫憫悙憭敃枛搾搾搾搾彂暀殭棖枙枙枙枙摀摀摀摀棗晹搾悙憭憭憭憭憫憫憫憫彁憮摃枟挀挀挀挀崘敇櫂枖晼晼晼晼摀摀摀摀棖枖搼憪拺拺拺拺 ...
recon2.v
棖枖搼憪拺拺拺拺憫憫憫憫悙憭敃枛搾搾搾搾摃殱灊洑枙枙枙枙摀摀摀摀棗晹搾悙憭憭憭憭憫憫憫憫悙憭敃枛挀挀挀挀挄櫇灊洐晼晼晼晼摀摀摀摀棖枖搼憪拺拺拺拺憫憫憫憫悙憭敃枛搾搾搾搾憯槣潨殬枙枙枙枙摀摀摀摀棗晹搾悙憭憭憭憭憫憫憫憫彁憮摃枟挀挀挀挀悡棜湜櫁晼晼晼晼摀摀摀摀棖枖搼憪拺拺拺拺憫憫憫憫悙憭敃枛搾搾搾搾彂暀殭棖枙枙枙枙摀摀摀摀棗晹搾悙憭憭憭憭憫憫憫憫彁憮摃枟挀挀挀挀崘敇櫂枖晼晼晼晼摀摀摀摀棖枖搼憪拺拺拺拺 ...
test2.v
憮摂敄敀憯枑帋憪崐崚挀彂悙憫憦弿搻彂弶帎帡殱灍殨晽枟棜湕攼帊帋彁晼摀憥悜挃拸憪憯彂敁挃悕崕悞攼憴憦摂悢攼敃槣殯様枙拻憰槝棎摉晳悞敃摂搻彁敂悘憫敁拺悜摃強寧拻摂棜敀晻敆攺憱槚枠槖枛憦帠櫃棏摂搼憯棙櫀棔挀晼攺媿憯拹挀悙悙帎摉枒摍棐挃拹攽悡棞殸櫀槝攼憯殨晱崝敄晻枠槜枔憮枛拸憭摃拵挃拸悞摉晹摀敊晲彅憭憦悞湚湤殨殭枔敆棙棎挄晽晼憵様攽嫃悜憤憮憪妽彁搹帒悙摉枙敊殦挄晸弾媿槜摉槗挅挀挀晼攳憭摃拻枦枓憤崕帎彁憫憪 ...
recon1.v
棖枖搼憪拺拺拺拺憫憫憫憫悙憭敃枛搾搾搾搾摃殱灊洑枙枙枙枙摀摀摀摀棗晹搾悙憭憭憭憭憫憫憫憫悙憭敃枛挀挀挀挀挄櫇灊洐晼晼晼晼摀摀摀摀棖枖搼憪拺拺拺拺憫憫憫憫悙憭敃枛搾搾搾搾憯槣潨殬枙枙枙枙摀摀摀摀棗晹搾悙憭憭憭憭憫憫憫憫彁憮摃枟挀挀挀挀悡棜湜櫁晼晼晼晼摀摀摀摀棖枖搼憪拺拺拺拺憫憫憫憫悙憭敃枛搾搾搾搾彂暀殭棖枙枙枙枙摀摀摀摀棗晹搾悙憭憭憭憭憫憫憫憫彁憮摃枟挀挀挀挀崘敇櫂枖晼晼晼晼摀摀摀摀棖枖搼憪拺拺拺拺 ...
test0.v
憭敂敃晵挄枑弾拺寠彃挀憫悜憭拸悘搼悞崏帎彇殲煙殨枠棗枤洍攼帋帋彁晻枔憥憫挃拹憪敂彁敀挃悕崕悢攼憵憦敂彅攽敄槣殰様枙拻憱櫂棌挄晵憭摃敂搻彁敂悘憭晹憭憪摃帇寧挀敂枤敀晹敄攺摉槜枡槕棖憦帟櫃枒摂搻憮棙棔棓挃敄枏嫀挃憪挀彁悜崙晼晵敋槖挄拹敀悢棝湡槚棙搹挄櫁晭帞晼晹枡槚枖憮枛拵悜敄搻摂拸悜挅晹敁敊晲彅憭拹悢洑湣殩殭枔敆槝晲挄晼晽挋棔晳寪悜憥憯拹妽彁攺帓悜摉枙晿殦挅晵弿妿槚摉檽挆拻挃晼晭挀敄拻枤槖拲帍帎彁憫憦 ...
test1.v
挃敃敃晵挄晳弾憫崐帓挃憫悙憫憦弿搻彂弶帒彇殲灋檿枠枛枤潡攼帋弾悙敃枔憥悜挄拸拹摂悙敁挃悗崕憭搹憵拸摂悢攽摉槣櫄檾枙憭憯槝枑挄晵憭敄敂搻彁敃悘悜晸悞憫摃帇實挀敂棜敀晻敆攺挅槜枡槖棖憦帠櫂枒摂搻憯棙槚棖挀敄晱實挃拹挀悙彂帒敄晳摎槖挄拸拺悡槢洜槚槝搹挃槚攷帞敃敂枡櫁枖憯枛拵悞敄搹摂搹彂挅敃敁摌攺彅拺悙悞洑湤殩殭枔敄槜攺挄枟摉憴様攽寪悜憥憮憫媿弿搹帓彁摉棔敇殦憱晵帋妽棖敃様憲拻摀晻搶悞敃挀暃棑拰帍帍悙憫憪 ...