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//????? //------------------------------------------------------------------------------ module adr(addr,fetch,ir_addr,pc_addr); output [12:0] addr; input [12:0] ir_addr, pc_addr; input fetch;

//---------------------------------------------------------------------------- module machine( inc_pc, load_acc, load_pc, rd,wr, load_ir, datactl_ena, halt, clk1, zero, ena, opcode ); output inc

module rom( data, addr, read, ena ); output [7:0] data; input [12:0] addr; input read, ena; reg [7:0] memory [13'h1fff:0]; wire [7:0] data; assign data= ( read && ena )? memory[addr] : 8'bzzzz

//------------------------------------------- cpu.v ????? ------------------------------------------- /****************************************************************************** *** ?????CP

//??? //-------------------------------------------------------------- module accum( accum, data, ena, clk1, rst); output[7:0]accum; input[7:0]data; input ena,clk1,rst; reg[7:0]accum; always@

//????? //------------------------------------------------------------------------------ module alu (alu_out, zero, data, accum, alu_clk, opcode); output [7:0]alu_out; output zero; input [7:0] da

// --------------- RAM?ROM ---------------------------------------- module ram( data, addr, ena, read, write ); inout [7:0] data; input [9:0] addr; input ena; input read, write; reg [7:0] ram [1

//????? //--------------------------------------------------------------- module register(opc_iraddr,data,ena,clk1,rst); output [15:0] opc_iraddr; input [7:0] data; input ena, clk1, rst; reg [15

//--------------?????---------------------- module addr_decode( addr, rom_sel, ram_sel); output rom_sel, ram_sel; input [12:0] addr; reg rom_sel, ram_sel; always @( addr ) begin casex(addr)

//------------------------------------------- cputop.v ????? ----------------------------------------------------- /*********************************************************************** *** ?????