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datapath.v
`include "Counter_128bits.v"
`include "memory.v"
`include "bidirec.v"
`include "Counter_State.v"
module DataPath(
Clk, //Clock
Sel, //Sel[0] ==> 0 ==> Mamery Address(A,B) ==> Counter_O
add.v
//`timescale 1ns/10ps
module Add(
InData_1,
InData_2,
OutData
);
parameter Data_Width = 20;
input [Data_Width-1:0] InData_1;
input [Data_Width-1:0] InData_2;
output [Data
vga.v
/*
vga(640*480, 60hz)
dclk=25M hs:Horizontal vs:Vertical
every Vertical has 525 Horizontals
every Horizontal has 800 point
IDEA BY XIAYANG
*/
module vga_drive(
//vga port///////////////
dpll.v
///////////2007.02.27 DPLL
module dpll(reset,clk,signal_in,signal_out,syn);//signalin=1.4us(best) to 1.28us,clk=10ns
parameter para_K=4;
parameter para_N=16;
input reset;
input clk;
input signal
counter.v
module counter(count_done, gnt_done, count_reset, Clk);
output count_done;
output gnt_done;
input count_reset;
input Clk;
reg [3:0]cnt, d_cnt;
wire gnt_done = (d_cnt < 4'b1001);
wire count_
arb.v
module arb(Gnt, Req, Clk, Reset_l);
output [3:0]Gnt;
input [3:0]Req;
input Clk;
input Reset_l;
wire count_reset, count_done, gnt_done;
arb_fsm myfsm(.Gnt(Gnt), .count_reset(count_reset), .
monitor.v
module monitor(Gnt, Clk, chk_coverage);
input Clk, chk_coverage;
input [3:0]Gnt;
reg err_flag, pass_flag;
reg [4:0] chk_state;
reg [24:0] chk_trans;
event ERR_EVENT, PASS_EVENT;
initial
xact.v
module xact(Req, chk_coverage, Clk, Reset_l, Gnt);
output [3:0]Req;
output Clk;
output Reset_l;
output chk_coverage;
input [3:0]Gnt;
reg [3:0]Req;
reg Clk, Reset_l;
reg chk_coverage;
reg
icpld.v
// Quartus Verilog Template
// Counter with synchronous load and active low asynchronous clear
module icpld (
input [2:0] SWITCH_MODE,RAM_ADDR_LATCH,
input [3:0] RAM_DATA_SEL,MCU_CODE,
in
vspi.v
// ----------------------------------------------------------------------
// Copyright 1997-1998 VAutomation Inc. Nashua NH USA.
// Visit HTTP://www.vautomation.com for mor details on our other
//