counter.v

一个用verilog编写的总线仲裁程序。多个设备共享总线

module counter(count_done, gnt_done, count_reset, Clk);

output count_done;
output gnt_done;
input count_reset;
input Clk;
reg [3:0]cnt, d_cnt;

wire gnt_done = (d_cnt < 4'b1001);
wire count_done = (d_cnt == 4'b1001);


always @(count_done or d_cnt)
  if(count_done)
    cnt <= 4'b0000;
  else
    cnt <= d_cnt + 4'b0001;

always @(negedge count_reset or posedge Clk)
  if(count_reset)
    d_cnt <= 4'b0000;
  else
    d_cnt <= cnt;


endmodule