arb.v

来自「一个用verilog编写的总线仲裁程序。多个设备共享总线」· Verilog 代码 · 共 18 行

module arb(Gnt, Req, Clk, Reset_l);

output [3:0]Gnt;
input [3:0]Req;
input Clk;
input Reset_l;

wire count_reset, count_done, gnt_done;

arb_fsm myfsm(.Gnt(Gnt), .count_reset(count_reset), .Req(Req), .Clk(Clk),
             .Reset_l(Reset_l), .count_done(count_done), .gnt_done(gnt_done));
counter mycounter(.count_done(count_done), .gnt_done(gnt_done),
                 .count_reset(count_reset), .Clk(Clk));

endmodule