xact.v

来自「一个用verilog编写的总线仲裁程序。多个设备共享总线」· Verilog 代码 · 共 77 行

module xact(Req, chk_coverage, Clk, Reset_l, Gnt);

output [3:0]Req;
output Clk;
output Reset_l;
output chk_coverage;
input [3:0]Gnt;

reg [3:0]Req;
reg Clk, Reset_l;
reg chk_coverage;
reg [31:0] random_number;

integer random_seed;
integer count;

initial 
begin
  Req <= 4'b0000;
  Clk <= 1'b0;
  Reset_l <= 1'b0;
  random_seed = 1;
  random_number <= 32'h0000_0000;
  count = 1;
  chk_coverage <= 1'b0;
end


initial
begin
  #5;
  Reset_l <= 1'b0;
  #100;
  Reset_l <= 1'b1;
  #10;
  random_number <= $random(random_seed);
  Req <= random_number[23:20];
  #60000;
  chk_coverage <= 1'b1;
  #100;
  $finish;
end

always 
#10  Clk <= ~Clk;

always @(negedge Clk)  
begin
  count = count + 1;
  if(count % 50 == 0)
    begin
    random_number <= $random(random_seed);
    Req <= random_number[23:20];
    end
end

always @(posedge Gnt[0])
    if(Req[0])
        Req[0] <= @(posedge Clk)1'b0;

always @(posedge Gnt[1])
    if(Req[1])
        Req[1] <= @(posedge Clk)1'b0;

always @(posedge Gnt[2])
    if(Req[2])
        Req[2] <= @(posedge Clk)1'b0;

always @(posedge Gnt[3])
    if(Req[3])
        Req[3] <= @(posedge Clk)1'b0;

endmodule