vga.v

vga 控制器的verilog 源码

/*
vga(640*480,    60hz) 
dclk=25M   hs:Horizontal  vs:Vertical
every Vertical has 525 Horizontals
every Horizontal has 800 point
IDEA BY XIAYANG
*/
module vga_drive(
//vga port////////////////////////////////////////////
					hs,			//vga hs
					vs,			//vga vs
					reset,		//reset
					clk,		//vga clk input 25M
					rgb_r,		//vga red output[9:0]
					rgb_b,		//
					rgb_g,		//
					blank,		//blank=hs&&vs
					vga_sync,	//tvsync=0
					vga_clk,	//clk to ad7123 25M
//sram port////////////////////////////////////////////
					sram_addr,  //sram address output[17:0]
					sram_data,  //sram data input[15:0]
					ce_n,       //
					we_n,
					lb_n,
					ub_n,
					oe_n
					);
////////////////////////////////////////////////////////
input clk,reset;
input[15:0] sram_data;
output[17:0] sram_addr;
output hs,vs,blank,vga_sync,vga_clk,ce_n,we_n,lb_n,ub_n,oe_n;
output[9:0] rgb_r,rgb_g,rgb_b;
reg hs,vs,ce_n,we_n,lb_n,ub_n,oe_n;
reg[9:0] rgb_r,rgb_b,rgb_g;
reg[17:0] sram_addr;
reg[9:0] h_cnt,v_cnt;
reg[1:0] h_state;
reg[1:0] v_state;
reg flage;							//control sram upper data or lower data
parameter video=0,front=1,sync=2,back=3;

assign blank=hs&&vs;				//blank
assign vga_sync=0;					//tvsync
assign vga_clk=clk;					//vga clk 25M
//////////////////////hs&vs(clk)///////////////////////////
always@(posedge clk or negedge reset)
begin
	if(!reset)
	begin
		h_cnt<=0;
		v_cnt<=0;
	end
	else if(h_cnt==799) 
	begin
		h_cnt<=0;
		if(v_cnt==524)
		begin
			v_cnt<=0;
		end
		else v_cnt<=v_cnt+1;
	end
	else h_cnt<=h_cnt+1;	
end
///////////////////////h_state////////////////////////
always @ (posedge clk or negedge reset)
begin 
	if(!reset) 
	begin
		sram_addr<=0;
		flage<=0;
	end
	else 
	begin
		case(h_state)
		video:						//video state
		begin
			hs<=1;
/////////////////control display//////////////////////
			we_n<=1;
			ce_n<=0;
			oe_n<=0;
			lb_n<=0;
			ub_n<=0;
			if(h_cnt%2)
			begin
				if(v_cnt<480) sram_addr<=v_cnt*320+h_cnt/2;
				else
				begin
					rgb_r[9:2]<=sram_data[7:0];
					rgb_g[9:2]<=sram_data[7:0];
					rgb_b[9:2]<=sram_data[7:0];		
				end		
			end
			else 
			begin
				rgb_r[9:2]<=sram_data[15:8];
				rgb_g[9:2]<=sram_data[15:8];
				rgb_b[9:2]<=sram_data[15:8];				
			end
//////////////////////////////////////////////////////		
			if(h_cnt==639) h_state<=front;											
			else	h_state<= video;
		end
	
		front:						// front porch
		begin
			hs<=1;
			rgb_r<=0;
			rgb_g<=0;
			rgb_b<=0;
			if(h_cnt==658) h_state<=sync;
			else	h_state<= front;
		end
	
		sync:						//sync pulse
		begin
			hs<=0;
			rgb_r<=0;
			rgb_g<=0;
			rgb_b<=0;	
			if(h_cnt==754) h_state<=back;
			else	h_state<= sync;
		end
	
		back:						//back porch
		begin
			hs<=1;
			rgb_r<=0;
			rgb_g<=0;
			rgb_b<=0;
			if(h_cnt==799) h_state<=video;
			else	h_state<= back;
		end
	
		default: h_state<=video;
		endcase
	end
end
//////////////////////v_state/////////////////////
always@(posedge clk)
begin
	case(v_state)				
	video: 						//video state
	begin
		vs<=1;
		if(v_cnt==479) v_state<=front;
		else	v_state<= video;
	end
	
	front:						//front proch	
	begin
		vs<=1;
		if(v_cnt==492) v_state<=sync;
		else	v_state<= front;
	end
	
	sync:						//sync pulse
	begin
		vs<=0;
		if(v_cnt==494) v_state<=back;
		else	v_state<= sync;
	end
	
	back:						//back porch
	begin
		vs<=1;
		if(v_cnt==524) v_state<=video;
		else v_state<= back;
	end
	
	default: v_state<=video;
	endcase
end

endmodule