datapath.v

這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder

`include "Counter_128bits.v"
`include "memory.v"
`include "bidirec.v"
`include "Counter_State.v"

module DataPath(
		Clk,			//Clock
		Sel,			//Sel[0] ==> 0 ==> Mamery Address(A,B) ==> Counter_Out
					//		   Mamery InData(A,B)  ==> Bidirec_inp
					//		   Mamery Wen(A,B)     ==> Print Control
					//Sel[0] ==> 1 ==> Mamery Address(A,B) ==> DWT_Memory_(A,B)_Address
					//Sel[1] ==> 0 ==> bidirec(inp) <== Memory_Out_Data(A)
					//Sel[1] ==> 1 ==> bidirec(inp) <== Memory_Out_Data(B)
                We_Memory_A,		//[0:0]
                Q_Memory_A_OutData,	//[7:0]
                
                We_Memory_B,		//[0:0]
                Q_Memory_B_OutData,	//[7:0]
                
                Wen_Counter_128bits,	//[0:0]
                Reset_Counter_128bits,	//[0:0]
                Done_Counter_128bits,	//[0:0]
                
                Wen_Counter_State,	//[0:0]	
                Reset_Counter_State,	//[0:0]
                Done_Counter_State,	//[0:0]

                DWT_Memory_A_Address,	//[13:0]
                DWT_Memory_B_Address,	//[13:0]
                DWT_Memory_A_InData,	//[7:0]
                DWT_Memory_B_InData,	//[7:0]
                
                Oe_Bidirec,		//[0:0]
                bidir			//[7:0]
                );

parameter Data_Width = 20;	//Data Width
parameter Address_Width = 12;	//Address Width 12bits = 4096
parameter OutData_Width = 8;	//Output Data Width

input		Clk;			
input	[1:0]	Sel;                        

                        
input				We_Memory_A;
output	[Data_Width-1:0]	Q_Memory_A_OutData;
                        
input				We_Memory_B;
output	[Data_Width-1:0]	Q_Memory_B_OutData;
                        
input				Wen_Counter_128bits;
input				Reset_Counter_128bits;
output				Done_Counter_128bits;

input				Wen_Counter_State;
input				Reset_Counter_State;
output				Done_Counter_State;

input	[Address_Width-1:0]	DWT_Memory_A_Address;
input	[Address_Width-1:0]	DWT_Memory_B_Address;
input	[Data_Width-1:0]	DWT_Memory_A_InData;
input	[Data_Width-1:0]	DWT_Memory_B_InData;
                      
input				Oe_Bidirec;
inout	[OutData_Width-1:0]	bidir;

reg	[Data_Width-1:0]	Q_Memory_A_OutData;
reg	[Address_Width-1:0]	Out_Counter_128bits; 
reg				Done_Counter_128bits;


wire	[OutData_Width-1:0]	Outp_Bidirec;



wire	[Address_Width-1:0]	Temp_Memory_A_Address = Sel[0] ? DWT_Memory_A_Address : Out_Counter_128bits;
wire	[Address_Width-1:0]	Temp_Memory_B_Address = Sel[0] ? DWT_Memory_B_Address : Out_Counter_128bits;
wire	[Data_Width-1:0]	Temp_Memory_A_InData  = Sel[0] ? DWT_Memory_A_InData  : {4'h0,Outp_Bidirec,8'h00};
wire	[Data_Width-1:0]	Temp_Memory_B_InData  = Sel[0] ? DWT_Memory_B_InData  :	{4'h0,Outp_Bidirec,8'h00};
wire	[OutData_Width-1:0]	Temp_Bidirec_Inp      = Sel[1] ? Q_Memory_A_OutData[Data_Width-5:Data_Width-12] : Q_Memory_B_OutData[Data_Width-5:Data_Width-12];


memory 	     A(
		.address(Temp_Memory_A_Address),
		.we(We_Memory_A),
		.inclock(Clk),
		.data(Temp_Memory_A_InData),
		.q(Q_Memory_A_OutData)
		);

memory 	     B(
		.address(Temp_Memory_B_Address),
		.we(We_Memory_B),
		.inclock(Clk),
		.data(Temp_Memory_B_InData),
		.q(Q_Memory_B_OutData)
		);

Counter_128bits C1(
		.Clk(Clk),			//Clock
	      	.Wen(Wen_Counter_128bits),	//Wen = 1 ==> Write
	      	.Reset(Reset_Counter_128bits),	//Reset Counter
	      	.Out_Count(Out_Counter_128bits),//Output Counter
	      	.Done(Done_Counter_128bits)	//Done = 1 ==> End
	      	);

bidirec		C2(	
		.oe(Oe_Bidirec),		//oe = 0 ==> output bidir, oe = 1 ==> input bidir
		.clk(Clk),			//Clock
		.inp(Temp_Bidirec_Inp),		//Data in
		.outp(Outp_Bidirec),		//Data out
		.bidir(bidir)
		);				// duport

Counter_State	C3(
		.Clk(Clk),			//Clock            
		.Wen(Wen_Counter_State),	//Wen = 1 ==> Write
		.Reset(Reset_Counter_State),	//Clear Counter    
		.Done(Done_Counter_State)	//Out Count == End 
		);
endmodule