register_i.v

来自「這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder」· Verilog 代码 · 共 38 行

//`timescale 1ns/10ps
module Register_I(
	Clk,
	Clr,
	Wen,
	Data_In,
	
	Out_Data

	);

parameter Data_Width = 20;

input		Clk;
input		Clr;
input		Wen;
input	[Data_Width-1:0]	Data_In;
	
output	[Data_Width-1:0]	Out_Data;

reg	[Data_Width-1:0]	Reg_R;


assign Out_Data = Reg_R;

always @(negedge Clk) begin
//always @(posedge Clk) begin
	if(!Clr)	//if Clr == 0, Clear Register
		Reg_R = 0;
	else begin
		if(Wen)	//Wen == 1, Write in Register
			Reg_R = Data_In;
		else
			Reg_R = Reg_R;
	end
end

endmodule