bidirec.v

来自「這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder」· Verilog 代码 · 共 30 行

module bidirec (oe,		//oe = 0 ==> bidir to outp, oe = 1 ==> inp to bidir
		clk,		//Clock
		inp,		//Data in
		outp,		//Data out
		bidir);		// duport

// Port Declaration

input   oe;
input   clk;
input   [7:0] inp;
output  [7:0] outp;
inout   [7:0] bidir;

reg     [7:0] a;
reg     [7:0] b;

assign bidir = oe ? a : 8'bZ ;
assign outp  = b;

// Always Construct

always @ (posedge clk)
begin
	b <= bidir;
	a <= inp;
end

endmodule