counter_128bits.v

来自「這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder」· Verilog 代码 · 共 41 行

module Counter_128bits(Clk,	        
		      Wen,	        
		      Reset,	        
		      Out_Count,        
		      Done);	        

parameter Address_Width = 12;
parameter End_1 = 4096;	//64 * 64 = 4096

input	Clk;
input	Wen;
input	Reset;

output				Done;
output	[Address_Width+1:0]	Out_Count;
reg				Done;
reg	[Address_Width+1:0]	Out_Count;

always @(posedge Clk or negedge Reset)
begin
	if(!Reset) begin
		Out_Count = 0;
		Done = 0;
	end
	else begin
//		if(Out_Count == End_1)
//			Done = 1;

//		else begin
			if(Wen)
				Out_Count = Out_Count + 1;
			else
				Out_Count = Out_Count;
//		end
	end
	
	
end

endmodule