counter_state.v

来自「這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder」· Verilog 代码 · 共 39 行

module Counter_State(	Clk,		//Clock
			Wen,		//Wen = 1 ==> Write
			Reset,		//Clear Counter
			Done);		//Out Count == End

parameter Delay_Time = 20;
parameter Delay = 5;

input	Clk;
input	Wen;                                     
input	Reset;
                                                             
output	Done;
reg	Done;
reg	[Delay-1:0]	Out_Count;
                                                             

                                                             
always @(posedge Clk)
begin
	if(!Reset) begin
		Out_Count = 0;
		Done = 0;
	end
	else begin
		if(Out_Count == Delay_Time)
			Done = 1;
		else begin
			if(Wen)
				Out_Count = Out_Count + 1;
			else
				Out_Count = Out_Count;
		end
	end

                                 
end                                                          
                                                             
endmodule