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V 的代码
savesegreg.v
module SaveSegReg( CLKM, ResetN,
//input
Init_Mem_End, RegBusy, RxNewSeg, Seg_Num,
EndAddr, RT_RDB, TxSeg,
//output
frbuf.v
/*******************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation o
pcrctl.v
module PCRCtl( ResetN, CLKM, CLK90K,
PCRn,NxtPCRn,
Fsync, Send_0SEG,
PCRnV, RdEnd, Pause,
TxEn,
//debug
rxinfofr.v
module RxInfoFr( CLKM, ResetN,
//input
bInfo, Fsync, Den, Rx_DB, Init_Mem_End, CompNewSeg_End, first_key,
//output
Init_Mem, RxN
dzfifo.v
`include "rxmodule.v"
`include "txmodule.v"
`include "kswitch.v"
`include "addrreg.v"
`include "csm1.v"
`include "pcrctl.v"
`include "pcrreg.v"
`include "div.v"
`include
comppid.v
module CompPID( CLKM, ResetN, // ResetN = ResetN & !K
//input
Rx_PID, Info_PID, Video_PID, Audio_PID,
PIDT_DB, CompDZTS_en,
//outp
kswitch.v
module KSwitch( K, CLKM,
DI, VALIDI, FSYNCI,
DO, VALIDO, FSYNCO,
FIFO_MDO, FIFO_DVALID, FIFO_FSYNC);
input K;
input [7:0] DI;
input [7:
csm.v
module csm( CLKM, ResetN,
//RxModule
RxData, RxFsync, RxDen, RxDaMux,
//CompPID
bProg,
//SaveSegReg
SaveEn,
ctlfb.v
module CtlFB( CLKM, ResetN,
//input
SaveBufFull, EPGTxEnd,
//output
BufEmpty, EPGTxEn, WRCS, RDCS
);
input CLKM;
in
pcraddrreg.v
module PCRAddrReg( CLKM, ResetN,
//input
IncEn, NxtFrame, SegAddr, Init_Mem_End, FindPCRSegA_End, Max_Seg_Num,
//output