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clock_edge.v
module clock_edge (clk_50M, clk_100M, rst_, cnt1, cnt2);
input clk_50M, clk_100M, rst_;
output [3:0] cnt1, cnt2;
reg [3:0] cnt_temp1, cnt_temp2, cnt2;
wire [3:0] cnt1;
always @ (p
clock_edge_tb.v
module clock_edge_tb ( );
reg clk_50M_temp, clk_100M, rst_;
wire clk_50M;
wire [3:0] cnt1, cnt2;
initial
begin
clk_50M_temp = 0;
clk_100M = 0;
clock_edge.v
module clock_edge (clk_50M, clk_100M, rst_, cnt1, cnt2);
input clk_50M, clk_100M, rst_;
output [3:0] cnt1, cnt2;
reg [3:0] cnt_temp1, cnt_temp2, cnt2;
wire [3:0] cnt1;
always @ (p
clock_edge.v
module clock_edge (clk_50M, clk_100M, rst_, cnt1, cnt2);
input clk_50M, clk_100M, rst_;
output [3:0] cnt1, cnt2;
reg [3:0] cnt_temp1, cnt_temp2, cnt2;
wire [3:0] cnt1;
always @ (p
clock_edge_tb.v
module clock_edge_tb ( );
reg clk_50M_temp, clk_100M, rst_;
wire clk_50M;
wire [3:0] cnt1, cnt2;
initial
begin
clk_50M_temp = 0;
clk_100M = 0;
mpi.v
// - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Verilog Design & Verification
// EDA Pioneer
// - - - - - - - - - - - - - - - - - - - - - - - - - - - -
`times
nortestbench.v
// - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Verilog HDL Design & Verification
// EDA Pioneer
// - - - - - - - - - - - - - - - - - - - - - - - - - - - -
`tim
stm.v
// - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Verilog Design & Verification
// EDA Pioneer
// - - - - - - - - - - - - - - - - - - - - - - - - - - - -
`timesca
spram.v
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: SPRAM.v
//
complex_bibus.v
module complex_bibus (clk, rst, sel1, sel2, sel3, data_bus, addr);
input clk, rst;
input sel1, sel2, sel3;
input [7:0] addr;
inout [7:0] data_bus;
wire [7:0] data_in;
reg [7:0] da