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V 的代码
mux2.v
module mux (en, a, b, mux_out);
input en;
input a, b;
output mux_out;
wire mux_out;
assign mux_out = (en)? a : b;
endmodule
clk_div_phase_tb.v
`timescale 1ns/1ps
module clk_div_phase_tb;
reg clk_200K;
reg rst;
wire clk_100K, clk_50K, clk_25K;
initial
begin
rst = 0;
clk_200K = 0;
# 10;
clk_div_phase.v
module clk_div_phase (rst, clk_200K, clk_100K, clk_50K, clk_25K);
input clk_200K;
input rst;
output clk_100K, clk_50K, clk_25K;
wire clk_100K, clk_50K, clk_25K;
re
clk_3div.v
module clk_3div (clk,reset,clk_out);
input clk, reset;
output clk_out;
reg[1:0] state;
reg clk1;
always @(posedge clk or negedge reset)
if(!reset)
state
clk_3div_tb.v
`timescale 1ns/1ps
module clk_3div_tb;
reg clk;
reg rst_;
wire clk_3div;
initial
begin
rst_ = 0;
clk = 0;
# 10;
rst_ = 1;
# 1000;
decode_cmb2.v
module decode_cmb2 (addr, CS, cs1, cs2, cs3, cs4);
input [7:0] addr; // only the 2 MSB bits used
input CS; // Low effect
output cs1, cs2, cs3, cs4; // Low effect
wire cs1,
decode_cmb_tb.v
`timescale 1ns/100ps
module decode_cmb_tb;
reg [7:0] addr; // only the 2 MSB bits used
reg CS; // Low effect
wire cs1a, cs2a, cs3a, cs4a; // Low effect
wire cs1b, cs2b, cs3b
decode_cmb2.v
module decode_cmb2 (addr, CS, cs1, cs2, cs3, cs4);
input [7:0] addr; // only the 2 MSB bits used
input CS; // Low effect
output cs1, cs2, cs3, cs4; // Low effect
wire cs1,
decode_cmb.v
module decode_cmb (addr, CS, cs1, cs2, cs3, cs4);
input [7:0] addr; // only the 2 MSB bits used
input CS; // Low effect
output cs1, cs2, cs3, cs4; // Low effect
reg cs1, cs
decode_cmb_tb.v
`timescale 1ns/100ps
module decode_cmb_tb;
reg [7:0] addr; // only the 2 MSB bits used
reg CS; // Low effect
wire cs1a, cs2a, cs3a, cs4a; // Low effect
wire cs1b, cs2b, cs3b