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reg_counter.v
module reg_counter (clock, reset_, cnt_reg_s, cnt_reg_a);
input clock;
input reset_;
output [3:0] cnt_reg_s;
output [3:0] cnt_reg_a;
reg [3:0] cnt_reg_s; //asynchronous reset
tb.v
`timescale 1ns/100ps
module tb;
reg [3:0] a ;
reg [3:0] b ;
wire [4:0] sum ;
initial begin
a = 0;
b = 0;
# 5
a = 'ha ;
# 1
b = 'h3 ;
a = 'he ;
# 1
a = 'hf ;
# 1
b = 1 ;
# 5;
a = 2
tb.v
`timescale 1ns/100ps
module tb;
reg [3:0] a ;
reg [3:0] b ;
wire [4:0] sum ;
initial begin
a = 0;
b = 0;
# 5
a = 'ha ;
# 1
b = 'h3 ;
a = 'he ;
# 1
a = 'hf ;
# 1
b = 1 ;
# 5;
a = 2
tb.v
`timescale 1ns/100ps
module tb;
reg [3:0] a ;
reg [3:0] b ;
wire [4:0] sum ;
initial begin
a = 0;
b = 0;
# 5
a = 'ha ;
# 1
b = 'h3 ;
a = 'he ;
# 1
a = 'hf ;
# 1
b = 1 ;
# 5;
a = 2
tb.v
`timescale 1ns/100ps
module tb;
reg [3:0] a ;
reg [3:0] b ;
wire [4:0] sum ;
initial begin
a = 0;
b = 0;
# 5
a = 'ha ;
# 1
b = 'h3 ;
a = 'he ;
# 1
a = 'hf ;
# 1
b = 1 ;
# 5;
a = 2
asyn_rst_syn_release.v
module asyn_rst_syn_release(clk, rst_, cnt1, cnt2);
input clk;
input rst_;
output [4:0] cnt1 , cnt2;
reg [4:0] cnt1 , cnt2;
// reset release circuit
reg reset_reg;
always @
asyn_rst.v
module asyn_rst (clk, rst_, cnt1, cnt2);
input clk;
input rst_;
output [4:0] cnt1 , cnt2;
reg [4:0] cnt1 , cnt2;
always @ (posedge clk or negedge rst_)
if (!rst_)
syn_rst.v
module syn_rst (clk, rst_, cnt1, cnt2);
input clk;
input rst_;
output [4:0] cnt1 , cnt2;
reg [4:0] cnt1 , cnt2;
always @ (posedge clk)
if (!rst_)
begin
mpi.v
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// Verilog Design & Verification
// EDA Pioneer
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`times
nortestbench.v
// - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Verilog Design & Verification
// EDA Pioneer
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`timesca