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stm.v
// - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Verilog Design & Verification
// EDA Pioneer
// - - - - - - - - - - - - - - - - - - - - - - - - - - - -
`timesca
spram.v
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: SPRAM.v
//
fulladd.v
module HalfAdd (X, Y, SUM, C_out);//半加器模块
input X;
input Y;
output SUM;
output C_out;
assign SUM = X ^ Y ;
assign C_out = X & Y ;
endmodule
module FullAdd (X, Y, C_in, SUM, C_out);//全加器模块
i
srl2pal.v
module srl2pal (clk, rst, srl_in, pal_out);
input clk;
input rst;
input srl_in;
output [7:0] pal_out;
reg [7:0] pal_out;
always @ (posedge clk or negedge rst)
if
srl2pal.v
module srl2pal (clk, rst, srl_in, pal_out);
input clk;
input rst;
input srl_in;
output [7:0] pal_out;
reg [7:0] pal_out;
always @ (posedge clk or negedge rst)
if
resource_share2.v
module resource_share2 (data_in,square);
input [7:0] data_in; //输入是补码
output [15:0] square;
wire [7:0] data_tmp;
assign data_tmp = (data_in[7])? (~data_in + 1) : data_in;
assign squ
resource_share1.v
module resource_share1 (data_in,square);
input [7:0] data_in; //输入是补码
output [15:0] square;
wire [7:0] data_bar;
assign data_bar = ~data_in + 1;
assign square=(data_in[7])? (data_bar*
mux.v
module mux (en, a, b, c, d, mux_out);
input [1:0] en;
input a, b, c, d;
output mux_out;
reg mux_out;
always @ (en or a or b or c or d)
case(en)
2'b00: mux_ou
mux.v
module mux (en, a, b, c, d, mux_out);
input [1:0] en;
input a, b, c, d;
output mux_out;
reg mux_out;
always @ (en or a or b or c or d)
case(en)
2'b00: mux_ou
mux2.v
module mux (en, a, b, mux_out);
input en;
input a, b;
output mux_out;
wire mux_out;
assign mux_out = (en)? a : b;
endmodule