fifo_generator_v2_0.v

Reed-Solomon 信道编码广泛应用于DVB中

/* 
 * $RDCfile: $ $Revision: 1.1.4.3 $ $Date: 2004/11/03 17:37:19 $
 *******************************************************************************
 * 
 * FIFO Generator v2.0 - Verilog Behavioral Model
 * 
 *******************************************************************************
 * 
 * Copyright(C) 2004 by Xilinx, Inc. All rights reserved.
 * This text/file contains proprietary, confidential
 * information of Xilinx, Inc., is distributed under
 * license from Xilinx, Inc., and may be used, copied
 * and/or disclosed only pursuant to the terms of a valid
 * license agreement with Xilinx, Inc. Xilinx hereby
 * grants you a license to use this text/file solely for
 * design, simulation, implementation and creation of
 * design files limited to Xilinx devices or technologies.
 * Use with non-Xilinx devices or technologies is expressly
 * prohibited and immediately terminates your license unless
 * covered by a separate agreement.
 *
 * Xilinx is providing theis design, code, or information
 * "as-is" solely for use in developing programs and 
 * solutions for Xilinx devices, with no obligation on the 
 * part of Xilinx to provide support. By providing this design, 
 * code, or information as one possible implementation of
 * this feature, application or standard. Xilinx is making no
 * representation that this implementation is free from any
 * claims of infringement. You are responsible for obtaining
 * any rights you may require for your implementation.
 * Xilinx expressly disclaims any warranty whatsoever with
 * respect to the adequacy of the implementation, including
 * but not limited to any warranties or representations that this 
 * implementation is free from claims of infringement, implied
 * warranties of merchantability or fitness for a particular
 * purpose.
 *
 * Xilinx products are not intended for use in life support
 * appliances, devices, or systems. Use in such applications is 
 * expressly prohibited.
 *
 * This copyright and support notice must be retained as part 
 * of this text at all times. (c)Copyright 1995-2004 Xilinx, Inc.
 * All rights reserved.
 * 
 *******************************************************************************
 * 
 * Filename: fifo_generator_v2_0_bhv.v
 * 
 * Description:
 *  THe verilog behavioral model for the FIFO generator core.
 * 
 *******************************************************************************
 */

`timescale 1ns/10ps


/*******************************************************************************
 * Declaration of top-level module
 ******************************************************************************/

module FIFO_GENERATOR_V2_0 
  (
   BACKUP, 
   BACKUP_MARKER, 
   CLK,
   DIN, 
   PROG_EMPTY_THRESH, 
   PROG_EMPTY_THRESH_ASSERT, 
   PROG_EMPTY_THRESH_NEGATE, 
   PROG_FULL_THRESH, 
   PROG_FULL_THRESH_ASSERT, 
   PROG_FULL_THRESH_NEGATE, 
   RD_CLK, 
   RD_EN, 
   RD_RST,
   RST, 
   WR_CLK,
   WR_EN, 
   WR_RST, 
   
   ALMOST_EMPTY, 
   ALMOST_FULL, 
   DATA_COUNT, 
   DOUT, 
   EMPTY, 
   FULL, 
   OVERFLOW, 
   PROG_EMPTY,
   PROG_FULL, 
   RD_DATA_COUNT, 
   UNDERFLOW, 
   VALID,
   WR_ACK, 
   WR_DATA_COUNT
   );

/******************************************************************************
 * Definition of Ports
 * 
 * 
 *****************************************************************************
 * Definition of Parameters 
 * 
 * 
 *****************************************************************************/

/******************************************************************************
 * Declare user parameters and their defaults
 *****************************************************************************/
 parameter  C_COMMON_CLOCK            = 0;
 parameter  C_COUNT_TYPE              = 0;
 parameter  C_DATA_COUNT_WIDTH        = 2;
 parameter  C_DEFAULT_VALUE           = "";
 parameter  C_DIN_WIDTH               = 8;
 parameter  C_DOUT_RST_VAL            = "";
 parameter  C_DOUT_WIDTH              = 8;
 parameter  C_ENABLE_RLOCS            = 0;
 parameter  C_FAMILY                  = "virtex2"; //Not allowed in Verilog model
 parameter  C_HAS_ALMOST_EMPTY        = 0;
 parameter  C_HAS_ALMOST_FULL         = 0;
 parameter  C_HAS_BACKUP              = 0;
 parameter  C_HAS_DATA_COUNT          = 0;
 parameter  C_HAS_MEMINIT_FILE        = 0;
 parameter  C_HAS_OVERFLOW            = 0;
 parameter  C_HAS_RD_DATA_COUNT       = 0;
 parameter  C_HAS_RD_RST              = 0;
 parameter  C_HAS_RST                 = 0;
 parameter  C_HAS_UNDERFLOW           = 0;
 parameter  C_HAS_VALID               = 0;
 parameter  C_HAS_WR_ACK              = 0;
 parameter  C_HAS_WR_DATA_COUNT       = 0;
 parameter  C_HAS_WR_RST              = 0;
 parameter  C_IMPLEMENTATION_TYPE     = 0;   
 parameter  C_INIT_WR_PNTR_VAL        = 0;
 parameter  C_MEMORY_TYPE             = 1;
 parameter  C_MIF_FILE_NAME           = "";
 parameter  C_OPTIMIZATION_MODE       = 0;
 parameter  C_OVERFLOW_LOW            = 0;
 parameter  C_PRELOAD_LATENCY         = 1;
 parameter  C_PRELOAD_REGS            = 0;
 parameter   C_PRIM_FIFO_TYPE         = 512;
 parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL       = 0;
 parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL       = 0;
 parameter  C_PROG_EMPTY_TYPE       = 0;
 parameter  C_PROG_FULL_THRESH_ASSERT_VAL        = 0;
 parameter  C_PROG_FULL_THRESH_NEGATE_VAL        = 0;
 parameter  C_PROG_FULL_TYPE        = 0;
 parameter  C_RD_DATA_COUNT_WIDTH     = 2;
 parameter  C_RD_DEPTH                = 256;
 parameter  C_RD_PNTR_WIDTH           = 8;
 parameter  C_UNDERFLOW_LOW           = 0;
 parameter  C_VALID_LOW               = 0;
 parameter  C_WR_ACK_LOW              = 0;
 parameter  C_WR_DATA_COUNT_WIDTH     = 2;
 parameter  C_WR_DEPTH                = 256;
 parameter  C_WR_PNTR_WIDTH           = 8;
 parameter  C_WR_RESPONSE_LATENCY     = 1;


 //There are 3 Verilog behavioral models
 // 0 = Synchronous FIFO/ShiftRam FIFO
 // 1 = Asynchronous FIFO
 // 2 = FIFO16
 parameter  C_VERILOG_IMPL = (C_IMPLEMENTATION_TYPE==0 ? 0 : 
			      (C_IMPLEMENTATION_TYPE==1 ? 0 : 
			       (C_IMPLEMENTATION_TYPE==2 ? 1 : 
				(C_IMPLEMENTATION_TYPE==3 ? 2 : 1))));
 
 
/******************************************************************************
 * Declare Input and Output Ports
 *****************************************************************************/
 input                            CLK;
 input                            BACKUP;
 input                            BACKUP_MARKER;
 input [C_DIN_WIDTH-1:0]          DIN;
 input [C_RD_PNTR_WIDTH-1:0]      PROG_EMPTY_THRESH;
 input [C_RD_PNTR_WIDTH-1:0]      PROG_EMPTY_THRESH_ASSERT;
 input [C_RD_PNTR_WIDTH-1:0]      PROG_EMPTY_THRESH_NEGATE;
 input [C_WR_PNTR_WIDTH-1:0]      PROG_FULL_THRESH;
 input [C_WR_PNTR_WIDTH-1:0]      PROG_FULL_THRESH_ASSERT;
 input [C_WR_PNTR_WIDTH-1:0]      PROG_FULL_THRESH_NEGATE;
 input 			          RD_CLK;
 input 			          RD_EN;
 input 			          RD_RST;
 input 			          RST;
 input 			          WR_CLK;
 input 			          WR_EN;
 input 			          WR_RST;
   
 output 		          ALMOST_EMPTY;
 output 		          ALMOST_FULL;
 output [C_DATA_COUNT_WIDTH-1:0]  DATA_COUNT;
 output [C_DOUT_WIDTH-1:0] 	  DOUT;
 output 			  EMPTY;
 output 			  FULL;
 output 			  OVERFLOW;
 output 			  PROG_EMPTY;
 output 			  PROG_FULL;
 output 			  VALID;
 output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
 output 			  UNDERFLOW;
 output 			  WR_ACK;
 output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
  

  reg 		                  ALMOST_EMPTY;
  reg 		                  ALMOST_FULL;
  reg [C_DATA_COUNT_WIDTH-1:0]    DATA_COUNT;
  reg [C_DOUT_WIDTH-1:0] 	  DOUT;
  reg 			          EMPTY;
  reg 			          FULL;
  reg 			          OVERFLOW;
  reg 			          PROG_EMPTY;
  reg 			          PROG_FULL;
  reg 			          VALID;
  reg [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
  reg 			          UNDERFLOW;
  reg 			          WR_ACK;
  reg [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
 

 wire                            CLK_0;
 wire                            RD_CLK_1;
 wire                            RD_CLK_2;
 wire                            WR_CLK_1;
 wire                            WR_CLK_2;
 wire                            RST_0;
 wire                            RST_1;
 wire                            RST_2;
 wire [C_DIN_WIDTH-1:0]		 DIN_0;
 wire [C_DIN_WIDTH-1:0]		 DIN_1;
 wire [C_DIN_WIDTH-1:0]		 DIN_2;
 wire                            RD_EN_0;
 wire                            RD_EN_1;
 wire                            RD_EN_2;
 wire                            WR_EN_0;
 wire                            WR_EN_1;
 wire                            WR_EN_2;
 wire [C_RD_PNTR_WIDTH-1:0]      PROG_EMPTY_THRESH_0;
 wire [C_RD_PNTR_WIDTH-1:0]      PROG_EMPTY_THRESH_1;
 wire [C_RD_PNTR_WIDTH-1:0]      PROG_EMPTY_THRESH_2;
 wire [C_RD_PNTR_WIDTH-1:0]      PROG_EMPTY_THRESH_ASSERT_0;
 wire [C_RD_PNTR_WIDTH-1:0]      PROG_EMPTY_THRESH_ASSERT_1;
 wire [C_RD_PNTR_WIDTH-1:0]      PROG_EMPTY_THRESH_ASSERT_2;
 wire [C_RD_PNTR_WIDTH-1:0]      PROG_EMPTY_THRESH_NEGATE_0;
 wire [C_RD_PNTR_WIDTH-1:0]      PROG_EMPTY_THRESH_NEGATE_1;
 wire [C_RD_PNTR_WIDTH-1:0]      PROG_EMPTY_THRESH_NEGATE_2;
 wire [C_WR_PNTR_WIDTH-1:0]      PROG_FULL_THRESH_0;
 wire [C_WR_PNTR_WIDTH-1:0]      PROG_FULL_THRESH_1;
 wire [C_WR_PNTR_WIDTH-1:0]      PROG_FULL_THRESH_2;
 wire [C_WR_PNTR_WIDTH-1:0]      PROG_FULL_THRESH_ASSERT_0;
 wire [C_WR_PNTR_WIDTH-1:0]      PROG_FULL_THRESH_ASSERT_1;
 wire [C_WR_PNTR_WIDTH-1:0]      PROG_FULL_THRESH_ASSERT_2;
 wire [C_WR_PNTR_WIDTH-1:0]      PROG_FULL_THRESH_NEGATE_0;
 wire [C_WR_PNTR_WIDTH-1:0]      PROG_FULL_THRESH_NEGATE_1;
 wire [C_WR_PNTR_WIDTH-1:0]      PROG_FULL_THRESH_NEGATE_2;

   
 wire 		                 ALMOST_EMPTY_I_0;
 wire 		                 ALMOST_EMPTY_I_1;
 wire 		                 ALMOST_EMPTY_I_2;
 wire 		                 ALMOST_FULL_I_0;
 wire 		                 ALMOST_FULL_I_1;
 wire 		                 ALMOST_FULL_I_2;
 wire [C_DATA_COUNT_WIDTH-1:0]   DATA_COUNT_I_0;
 wire [C_DOUT_WIDTH-1:0]         DOUT_I_0;
 wire [C_DOUT_WIDTH-1:0]         DOUT_I_1;
 wire [C_DOUT_WIDTH-1:0]         DOUT_I_2;
 wire 			         EMPTY_I_0;
 wire 			         EMPTY_I_1;
 wire 			         EMPTY_I_2;
 wire 			         FULL_I_0;
 wire 			         FULL_I_1;
 wire 			         FULL_I_2;
 wire 			         OVERFLOW_I_0;
 wire 			         OVERFLOW_I_1;
 wire 			         OVERFLOW_I_2;
 wire 			         PROG_EMPTY_I_0;
 wire 			         PROG_EMPTY_I_1;
 wire 			         PROG_EMPTY_I_2;
 wire 			         PROG_FULL_I_0;
 wire 			         PROG_FULL_I_1;
 wire 			         PROG_FULL_I_2;
 wire 			         VALID_I_0;
 wire 			         VALID_I_1;
 wire 			         VALID_I_2;
 wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_I_1;
 wire 			         UNDERFLOW_I_0;
 wire 			         UNDERFLOW_I_1;
 wire 			         UNDERFLOW_I_2;
 wire 			         WR_ACK_I_0;
 wire 			         WR_ACK_I_1;
 wire 			         WR_ACK_I_2;
 wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_I_1;
  
fifo_generator_v2_0_bhv_ver_ss
  #(
    C_COMMON_CLOCK,
    C_COUNT_TYPE,
    C_DATA_COUNT_WIDTH,
    C_DEFAULT_VALUE,
    C_DIN_WIDTH,
    C_DOUT_RST_VAL,
    C_DOUT_WIDTH,
    C_ENABLE_RLOCS,
    C_FAMILY,//Not allowed in Verilog model
    C_HAS_ALMOST_EMPTY,
    C_HAS_ALMOST_FULL,
    C_HAS_BACKUP,
    C_HAS_DATA_COUNT,
    C_HAS_MEMINIT_FILE,
    C_HAS_OVERFLOW,
    C_HAS_RD_DATA_COUNT,
    C_HAS_RD_RST,
    C_HAS_RST,
    C_HAS_UNDERFLOW,
    C_HAS_VALID,
    C_HAS_WR_ACK,
    C_HAS_WR_DATA_COUNT,
    C_HAS_WR_RST,
    C_IMPLEMENTATION_TYPE,
    C_INIT_WR_PNTR_VAL,
    C_MEMORY_TYPE,
    C_MIF_FILE_NAME,
    C_OPTIMIZATION_MODE,
    C_OVERFLOW_LOW,
    C_PRELOAD_LATENCY,
    C_PRELOAD_REGS,
    C_PROG_EMPTY_THRESH_ASSERT_VAL,
    C_PROG_EMPTY_THRESH_NEGATE_VAL,
    C_PROG_EMPTY_TYPE,
    C_PROG_FULL_THRESH_ASSERT_VAL,
    C_PROG_FULL_THRESH_NEGATE_VAL,
    C_PROG_FULL_TYPE,
    C_RD_DATA_COUNT_WIDTH,
    C_RD_DEPTH,
    C_RD_PNTR_WIDTH,
    C_UNDERFLOW_LOW,
    C_VALID_LOW,
    C_WR_ACK_LOW,
    C_WR_DATA_COUNT_WIDTH,
    C_WR_DEPTH,
    C_WR_PNTR_WIDTH,
    C_WR_RESPONSE_LATENCY
  )
  gen_ss
  (
    .CLK(CLK_0), 
    .RST(RST_0), 
    .DIN(DIN_0), 
    .WR_EN(WR_EN_0), 
    .RD_EN(RD_EN_0), 
    .PROG_EMPTY_THRESH(PROG_EMPTY_THRESH_0), 
    .PROG_EMPTY_THRESH_ASSERT(PROG_EMPTY_THRESH_ASSERT_0), 
    .PROG_EMPTY_THRESH_NEGATE(PROG_EMPTY_THRESH_NEGATE_0), 
    .PROG_FULL_THRESH(PROG_FULL_THRESH_0), 
    .PROG_FULL_THRESH_ASSERT(PROG_FULL_THRESH_ASSERT_0), 
    .PROG_FULL_THRESH_NEGATE(PROG_FULL_THRESH_NEGATE_0), 
    .DOUT(DOUT_I_0), 
    .FULL(FULL_I_0), 
    .ALMOST_FULL(ALMOST_FULL_I_0), 
    .WR_ACK(WR_ACK_I_0), 
    .OVERFLOW(OVERFLOW_I_0), 
    .EMPTY(EMPTY_I_0), 
    .ALMOST_EMPTY(ALMOST_EMPTY_I_0), 
    .VALID(VALID_I_0), 
    .UNDERFLOW(UNDERFLOW_I_0), 
    .DATA_COUNT(DATA_COUNT_I_0), 
    .PROG_FULL(PROG_FULL_I_0), 
    .PROG_EMPTY(PROG_EMPTY_I_0)
   );

fifo_generator_v2_0_bhv_ver_as
  #(
    C_COMMON_CLOCK,