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V 的代码
frbufctl.v
`include "SaveFrameBuf.v"
`include "TxFrameBuf.v"
`include "CtlFB.v"
module FrBufCtl( CLKM, ResetN,
//input
bInfo, bProg, bDZTS, FValid, RxFsync, RxDen, Rx_D
wraddrreg.v
module WrAddrReg( CLKM, ResetN,
//input
IncEn, NxtFrame, SetNewSeg,
NewSegSA,
//output
WrAddr, New ,
txmodule.v
module TxModule( ResetN, CLKM,
//input
ProgData, ProgWrEn, ProgAddr, ProgTxEn,
EPGData, EPGWrEn, EPGAddr, EPGTxEn,
//output
keyreg.v
module KeyReg(first_key);
output [7:0] first_key;
assign first_key = 8'h92;
endmodule
addrconn.v
module addrconn( adi, cso, ado);
input [27:0] adi;
output [2:0] cso;
output [23:0] ado;
assign cso = adi[27:25];
assign ado = adi[24:1];
endmodule
rxmodule.v
module RxModule(RESETN, CLKM,
//input
MDI, VALIDI, FSYNCI, DMUX,
//output
DATA, FSYNCV, DEN,RX_PID,
//debug
rtctl.v
`include "OperMux.v"
`include "OperMux1.v"
`include "InitSegRegTab.v"
`include "SaveSegReg.v"
`include "WrAddrReg.v"
`include "GetPCRSegAddr.v"
`include "PCRAddrReg.v"
`include "GetTxSegAddr
gettxsegaddr.v
module GetTxSegAddr( CLKM, ResetN,
//input
RegBusy, TxSeg, FindTxSegA_En,
RT_RDB, RDPCR_EN,
//output
clkmod.v
module ClkMod(ResetN, CLK36M, CLK12M, CLK90K);
input ResetN;
input CLK36M;
output CLK12M;
output CLK90K;
reg [8:0] clk90cnt;
reg [5:0] clk12cnt;
assign CLK12M = clk12cnt[4];
assign C
pidctl.v
`include "ProgPidReg.v"
`include "CompPID.v"
module PIDCtl( CLKM, ResetN,
//input
I2C_PT_A, I2C_PT_DB, I2C_PT_WR, K, Rx_PID,
PIDT_DB, CompDZTS_en,