代码搜索结果
找到约 7,641 项符合
V 的代码
counter.v
module counter ( clock,
reset,
data_bus_in,
cnt_out
);
input clock, reset;
input [7:0] data_bu
complex_bibus2.v
module complex_bibus (clk, rst, sel1, sel2, sel3, data_bus, addr);
input clk, rst;
input sel1, sel2, sel3;
input [7:0] addr;
inout [7:0] data_bus;
wire [7:0] data_in;
//wire [7:0]
bibus.v
module bibus (clk, rst, sel, data_bus, addr);
input clk, rst, sel;
input [7:0] addr;
inout [7:0] data_bus;
wire [7:0] data_in, data_out;
assign data_in = data_bus;
assign data_bus = (sel
decode.v
module decode (clock, reset, data_bus_in, addr_bus, data_bus_out);
input clock, reset;
input [7:0] data_bus_in;
input [7:0] addr_bus;
output [7:0] data_bus_out;
reg [7:0] data_bu
complex_bibus.v
module complex_bibus (clk, rst, sel1, sel2, sel3, data_bus, addr);
input clk, rst;
input sel1, sel2, sel3;
input [7:0] addr;
inout [7:0] data_bus;
wire [7:0] data_in;
reg [7:0] da
counter.v
module counter ( clock,
reset,
data_bus_in,
cnt_out
);
input clock, reset;
input [7:0] data_bu
complex_bibus2.v
module complex_bibus (clk, rst, sel1, sel2, sel3, data_bus, addr);
input clk, rst;
input sel1, sel2, sel3;
input [7:0] addr;
inout [7:0] data_bus;
wire [7:0] data_in;
//wire [7:0]
decode.v
module decode (clock, reset, data_bus_in, addr_bus, data_bus_out);
input clock, reset;
input [7:0] data_bus_in;
input [7:0] addr_bus;
output [7:0] data_bus_out;
reg [7:0] data_bu
bibus.v
module bibus (clk, rst, sel, data_bus, addr);
input clk, rst, sel;
input [7:0] addr;
inout [7:0] data_bus;
wire [7:0] data_in, data_out;
assign data_in = data_bus;
assign data_bus = (sel
decode.v
module decode (clock, reset, data_bus_in, addr_bus, data_bus_out);
input clock, reset;
input [7:0] data_bus_in;
input [7:0] addr_bus;
output [7:0] data_bus_out;
reg [7:0] data_bu