eg7014 v1.0.v

用于fpga对EG7014液晶屏的刷新显示。avalone接口。

/*
程序说明:
用于fpga对EG7014液晶屏的刷新显示.版本1.0.完成于2008.4.14
*/
/*
使用说明:
实现方式是在SDRAM中开辟一段显示缓存。
程序每隔一定周期（分频clklcd=clkcount[3]时为1024个周期）读取一次显示数据用以刷新LCD。
parameter BASE_ADDRESS = 32'h0080_0000 ;用以规定显存起始地址。显存数为偏移量从0到3999的32位数据。
*/
module EG7014 
(
	input wire reset,
	input wire clk,
	input wire waitrequest,
	output reg[31:0] address,
	output reg read,
	input wire[31:0] readdata,
//////////////////////	
	output reg xscl,
	output reg lp,
	output reg yd,
	output wire doff1,
	output wire doff2,
	output reg[7:0] xd
);	
//-----------------------------------------------------------------------
	parameter BASE_ADDRESS = 32'h0080_0000 ;
//-----------------------------------------------------------------------	
	wire clklcd;
	reg[4:0] clkcount;	
	always@(posedge clk) begin
		clkcount<=clkcount+1;		
	end
	assign clklcd=clkcount[3];
/////////////////////////////////////
	assign doff1= reset ? 0 : 1;//为1时显示
	assign doff2= reset ? 0 : 1;
/////////////////////////////////////		
	reg[3:0] div;
	reg[6:0] x;
	reg[7:0] y;
	reg[13:0] count;
	always@(posedge clklcd or posedge reset) begin
		if(reset) begin
			div<=0;
			x<=0;
			y<=0;			
		end
		else begin
			div<=div+1;	
			if(div==15) begin
				if(x==80) begin
					x<=0;
					if(y==199)begin
						y<=0;
					end
					else begin
						y<=y+1;
					end					
				end
				else begin
					x<=x+1;
				end
			end
		end
	end	
///////////////////////		
	always@(posedge clklcd or posedge reset) begin
		if(reset) begin
			lp<=0;
			xscl<=0;
			yd<=0;
			count<=0;
		end
		else begin
			if(div==3) begin				
				if(x==80) begin
					lp<=1;
				end
				else begin
					xscl<=1;
					xd<=lcddata[x[2:0]];
					count<=count+1;
				end
			end
			else if(div==11) begin
				xscl<=0;
				lp<=0;
			end
			/////////////
			if((x==80) && (y==0)) begin
				if(div==0) begin
					yd<=1;
					count<=0;
				end
				else if(div==15) begin
					yd<=0;
				end	
			end	
		end	
	end
//-----------------------------------------------------------------------
	reg[7:0] lcddata[7:0];
	reg[5:0] readstate;
	always@(posedge clk or posedge reset) begin
		if(reset) begin
			readstate<=0;
			read<=0;
		end
		else begin
			case (readstate)
				0 : begin
					if(x[2:0]==1) begin
						readstate<=1;
						address<={BASE_ADDRESS[31:12],count[13:2]+1,2'b00};
						read<=1;
					end					
				end
				1 : begin
					if(waitrequest==0) begin
						{lcddata[4],lcddata[5],lcddata[6],lcddata[7]}<=readdata;						
						readstate<=2;
						read<=0;
					end
				end
				2 : begin
					if(x[2:0]==5) begin
						readstate<=3;
						if(count[13:2]>=3999) address<={BASE_ADDRESS[31:12],12'h000};
						else address<={BASE_ADDRESS[31:12],count[13:2]+1,2'b00};
						read<=1;
					end
				end
				3 : begin
					if(waitrequest==0) begin
						{lcddata[0],lcddata[1],lcddata[2],lcddata[3]}<=readdata;
						readstate<=0;
						read<=0;
					end
				end
			endcase
		end
	end
//-----------------------------------------------------------------------
endmodule