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up_bfm.v
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// Verilog HDL Design & Verification
// EDA Pioneer
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`tim
harness.v
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// Verilog HDL Design & Verification
// EDA Pioneer
// - - - - - - - - - - - - - - - - - - - - - - - - - - - -
`tim
spram.v
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: SPRAM.v
//
cnt3.v
module cnt2 (cnt_out, cnt_out_plus);
input [3:0] cnt_out;
output [3:0] cnt_out_plus;
wire [3:0] cnt_out_plus;
assign cnt_out_plus = cnt_out + 1;
endmodule
cnt1.v
module cnt1 (clock, cnt_out);
input clock;
output [3:0] cnt_out;
reg [3:0] cnt_out;
always @ (posedge clock)
cnt_out
cnt2.v
module cnt2 (cnt_out, cnt_out_plus);
input [3:0] cnt_out;
output [3:0] cnt_out_plus;
reg [3:0] cnt_out_plus;
always @ (cnt_out)
cnt_out_plus = cnt_out + 1;
endmodule
state2.v
//2-paragraph method to describe FSM
//Describe sequential state transition in 1 sequential always block
//State transition conditions in the other combinational always block
//Package state output
state1.v
//1-paragraph method to decribe FSM
//Describe state transition, state output, state input condition in only 1 always block
//Westor, Dec. 2006
//Verilog Usage Book
module state1 ( nrst,clk,
state3.v
//3-paragraph method to describe FSM
//Describe sequential state transition in the 1st sequential always block
//State transition conditions in the 2nd combinational always block
//Describe the FSM
state2_default.v
//Add a default state to make it more safe
module state2_default ( nrst,clk,
i1,i2,
o1,o2,
err
);
input nrst,cl