rgmii_gen_v3_0.v

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///////////////////////////////////////////////////////////////////////////////
//
//      Project:  RGMII Adaptation Module
//      Version:  1.0
//      File   :  rgmii_gen_v3_0.v
//
//      Company:  Xilinx
// Contributors:  Ting Kao, Mary Low
//
//   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
//                APPLICATION OR STANDARD, XILINX IS MAKING NO
//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
//                PURPOSE.
//
//                (c) Copyright 2003 Xilinx, Inc.
//                All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// RGMII Generation Module 
// Author: Ting Kao
// Translated to Verilog by Nigel Gulstone
//
// Description: RGMII Top Level module that combines the RGMII Transmit, 
//              RGMII Receive, and the Reset Synchronizer modules
//
///////////////////////////////////////////////////////////////////////////////

`timescale 1 ps / 1 ps	

module RGMII_GEN 
(
    // General signals
    RESET,                

   
    // RGMII Interface
    RGMII_RX_CTL_RISING,  
    RGMII_RX_CTL_FALLING, 
    RGMII_RXD_RISING,     
    RGMII_RXD_FALLING,    
    RGMII_RX_CLK,             
    RGMII_TX_CTL_RISING,  
    RGMII_TX_CTL_FALLING, 
    RGMII_TXD_RISING,     
    RGMII_TXD_FALLING,    
    RGMII_TX_CLK,         
    RGMII_RX_SPEED,       
    RGMII_RX_DUPLEX,      
    RGMII_LINK,           
    
    // GMII Interface   
    GTX_CLK,              
    GMII_TXD_FROM_CORE,   
    GMII_TX_EN_FROM_CORE, 
    GMII_TX_ER_FROM_CORE,     
    GMII_COL_TO_CORE,     
    GMII_CRS_TO_CORE,     
    GMII_RXD_TO_CORE,     
    GMII_RX_DV_TO_CORE,   
    GMII_RX_ER_TO_CORE,   
 
    // CLK generator output  
    TX_CORE_CLK,          
    RX_CORE_CLK           


);

//*****************************Parameter Declarations**************************

    parameter   SPEED_IS_10_100       = 1'b0;
    parameter   RX_HALF_DUPLEX        = 1'b0;
    parameter   TX_HALF_DUPLEX        = 1'b0;
    

//***********************************Port Declarations**************************

    // General signals
    input   	    RESET;                
    
    
    // RGMII Interface
    input           RGMII_RX_CTL_RISING;    
    input           RGMII_RX_CTL_FALLING;   
    input   [3:0]   RGMII_RXD_RISING;     
    input   [3:0]   RGMII_RXD_FALLING;    
    input           RGMII_RX_CLK;         
    
    output          RGMII_TX_CTL_RISING;  
    output          RGMII_TX_CTL_FALLING; 
    output  [3:0]   RGMII_TXD_RISING;     
    output  [3:0]   RGMII_TXD_FALLING;    
    output          RGMII_TX_CLK;         
    output  [1:0]   RGMII_RX_SPEED;       
    output          RGMII_RX_DUPLEX;      
    output          RGMII_LINK;           


    // GMII Interface
    input           GTX_CLK;              
    input   [7:0]   GMII_TXD_FROM_CORE;   
    input           GMII_TX_EN_FROM_CORE; 
    input           GMII_TX_ER_FROM_CORE; 
    
    output          GMII_COL_TO_CORE;     
    output          GMII_CRS_TO_CORE;     
    output  [7:0]   GMII_RXD_TO_CORE;     
    output          GMII_RX_DV_TO_CORE;   
    output          GMII_RX_ER_TO_CORE;   


    // CLK generator output    
    output          TX_CORE_CLK;          
    output          RX_CORE_CLK;           


//*********************************Wire Declarations***************************
    
    //Synchronized reset signals
    wire 	gmii_mii_tx_rst_i;
    wire 	gmii_mii_rx_rst_i;
    
    
    //Receiving and Transmitting Indicator Signals from converters
    wire 	receiving_i;
    wire 	transmitting_i;
    
    
    //Half duplex mode signal
    wire 	int_half_duplex_c;  
 
 
//*********************************Main Body of Code**********************************



    //_______________________Glue Logic for collision signals_________________________
    
    
    
    //If TX or RX is half duplex, switch to half duplex mode
    assign  int_half_duplex_c   =   RX_HALF_DUPLEX | TX_HALF_DUPLEX; 
      
     
     
    //Register a collition if while in half duplex mode an transmission
    // and reception happen simultaniously
    assign  GMII_COL_TO_CORE    =   (receiving_i & transmitting_i & int_half_duplex_c);
      
     
     
    //Assert CRS if Receiving or Transmitting ( What is CRS? )
    assign  GMII_CRS_TO_CORE    =   receiving_i | transmitting_i;
    
    
    
    //____________________Connect Output Clock Signals__________________________
        

    assign  RGMII_TX_CLK        =   GTX_CLK;
    assign  TX_CORE_CLK         =   GTX_CLK;
    assign  RX_CORE_CLK         =   RGMII_RX_CLK;
       
 
 
    
    //____________________Instantiate Synch Reset Modules ________________________
    
    
    //Synchronize the Global Reset with the tx clock 
    SYNC_RESET sync_gmii_mii_tx_reset_i
    (
        .RESET_IN(RESET), 
        .CLK(GTX_CLK),       
        .RESET_OUT(gmii_mii_tx_rst_i) 
    );


    
    //Syncronize the Global Reset with the rx clock
    SYNC_RESET sync_gmii_mii_rx_reset_i
    (
        .RESET_IN(RESET), 
        .CLK(RGMII_RX_CLK),       
        .RESET_OUT(gmii_mii_rx_rst_i) 
    );
 
  
 
    //_____________Instantiate RGMII to GMII Conversion Modules___________________
    
    
    
    
    // Convert GMII output from Transmitter to RGMII for PHY
    RGMII_TX    rgmii_txgen_i
    (
        //General Signals
        .RESET(gmii_mii_tx_rst_i),                     
        .CLK(GTX_CLK),                       
      
        
        //PHY Interface (RGMII)
        .RGMII_TX_CTL_RISING( RGMII_TX_CTL_RISING ),   
        .RGMII_TX_CTL_FALLING( RGMII_TX_CTL_FALLING ), 
        .RGMII_TXD_RISING( RGMII_TXD_RISING ),         
        .RGMII_TXD_FALLING( RGMII_TXD_FALLING ),       
        
        
        //Transmitter Interface (GMII)
        .GMII_TXD( GMII_TXD_FROM_CORE ),                  
        .GMII_TX_EN( GMII_TX_EN_FROM_CORE ),              
        .GMII_TX_ER( GMII_TX_ER_FROM_CORE ),              
        
        
        //Configuration and Indicators
        .SPEED_IS_10_100( SPEED_IS_10_100 ),         
        .TRANSMITTING( transmitting_i )                  
    );
  

  
    //Convert RGMII input from PHY to GMII for receiver 
    RGMII_RX    rgmii_rxgen_i
    (
        //General Signals
        .RESET( gmii_mii_rx_rst_i ),                     
        .RX_CLK( RGMII_RX_CLK ), 
        
        
        //RGMII Interface (Input)
        .RGMII_RX_CTL_RISING( RGMII_RX_CTL_RISING ),  
        .RGMII_RX_CTL_FALLING( RGMII_RX_CTL_FALLING ), 
        .RGMII_RXD_RISING( RGMII_RXD_RISING ),        
        .RGMII_RXD_FALLING( RGMII_RXD_FALLING ), 
        
        
        //GMII Interface (Output)
        .GMII_RXD( GMII_RXD_TO_CORE ),                
        .GMII_RX_DV( GMII_RX_DV_TO_CORE ),            
        .GMII_RX_ER( GMII_RX_ER_TO_CORE ),
        
        
        //Indicators from RGMII_RX
        .RGMII_RX_SPEED( RGMII_RX_SPEED ),             
        .RGMII_RX_DUPLEX( RGMII_RX_DUPLEX ),           
        .RGMII_LINK( RGMII_LINK ),                    
        .RECEIVING( receiving_i )                      
    );

endmodule