gmac_rgmii_v3_0.v

一个关于以太网MAC核和介质无关接口的原代码,希望对大家有帮助!

///////////////////////////////////////////////////////////////////////////////
//
//      Project:  RGMII/Gigabit Ethernet MAC
//      Version:  1.0
//      File   :  gmac_rgmii_v3_0.v
//
//      Company:  Xilinx
// Contributors:  Ting Kao, Mary Low
//
//   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
//                APPLICATION OR STANDARD, XILINX IS MAKING NO
//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
//                PURPOSE.
//
//                (c) Copyright 2003 Xilinx, Inc.
//                All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// Top Level RGMII Gigabit Ethernet MAC
// Author: Ting Kao
// Translated to Verilog by Mary Low
//
// Description: This is the top level module that combines the GMAC
//              and the RGMII Shim.
///////////////////////////////////////////////////////////////////////////////

`timescale 1 ps / 1 ps

module GMAC_RGMII
(    
    // Reset Signal
    RESET,  

    // Client Receiver Interface
    RX_CLK,               
    RX_GOOD_FRAME,        
    RX_BAD_FRAME,         
    RX_DATA,              
    RX_DATA_VALID,        
    RX_STATISTICS_VECTOR, 
    RX_STATISTICS_VALID,  
    
    // Client Transmitter Interface
    TX_CLK,               
    TX_DATA,              
    TX_DATA_VALID,        
    TX_UNDERRUN,          
    TX_ACK,              
    TX_RETRANSMIT,        
    TX_COLLISION,         
    TX_IFG_DELAY,         
    TX_STATISTICS_VECTOR, 
    TX_STATISTICS_VALID,  

    // MAC Control Interface
    PAUSE_REQ,          
    PAUSE_VAL,          

    // RGMII Interface
    GTX_CLK,              
    RGMII_TX_CTL_RISING,    
    RGMII_TX_CTL_FALLING,   
    RGMII_TXD_RISING,       
    RGMII_TXD_FALLING,    
    RGMII_TX_CLK,         
    RGMII_RX_CTL_RISING,    
    RGMII_RX_CTL_FALLING,   
    RGMII_RXD_RISING,       
    RGMII_RXD_FALLING,    
    RGMII_RX_SPEED,           
    RGMII_RX_DUPLEX,      
    RGMII_RX_CLK,         
    RGMII_LINK,           

    // MDIO Interface
    MDIO_IN,             
    MDIO_OUT,            
    MDIO_TRI,            
    MDC,                 

    // Host Interface
    HOST_CLK,        
    HOST_OPCODE,     
    HOST_ADDR,       
    HOST_WR_DATA,    
    HOST_REQ,        
    HOST_MIIM_SEL,   
    HOST_RD_DATA,    
    HOST_MIIM_RDY   
);  

//***********************************Port Declarations*************************

    // Reset Signal
    input	  	RESET; 
    
    // Client Receiver Interface
    output	 	RX_CLK;               
    output	 	RX_GOOD_FRAME;        
    output	 	RX_BAD_FRAME;         
    output [7:0] 	RX_DATA;              
    output	 	RX_DATA_VALID;        
    output [22:0]	RX_STATISTICS_VECTOR; 
    output	 	RX_STATISTICS_VALID;  
    
    // Client Transmitter Interface
    output	 	TX_CLK;               
    input  [7:0]	TX_DATA;              
    input		TX_DATA_VALID;        
    input		TX_UNDERRUN;          
    output		TX_ACK;              
    output		TX_RETRANSMIT;        
    output		TX_COLLISION;         
    input  [7:0]	TX_IFG_DELAY;         
    output [28:0]	TX_STATISTICS_VECTOR; 
    output		TX_STATISTICS_VALID;  

    // MAC Control Interface
    input		PAUSE_REQ;          
    input  [15:0]	PAUSE_VAL;          

    // RGMII Interface
    input		GTX_CLK;              
    output		RGMII_TX_CTL_RISING;    
    output		RGMII_TX_CTL_FALLING;   
    output [3:0]	RGMII_TXD_RISING;       
    output [3:0]	RGMII_TXD_FALLING;    
    output		RGMII_TX_CLK;         
    input		RGMII_RX_CTL_RISING;    
    input		RGMII_RX_CTL_FALLING;   
    input  [3:0]	RGMII_RXD_RISING;       
    input  [3:0]	RGMII_RXD_FALLING;    
    input		RGMII_RX_CLK; 
    output [1:0]	RGMII_RX_SPEED;           
    output		RGMII_RX_DUPLEX;              
    output		RGMII_LINK;           

    // MDIO Interface
    input		MDIO_IN;             
    output		MDIO_OUT;            
    output		MDIO_TRI;            
    output		MDC;                 

    // Host Interface
    input		HOST_CLK;        
    input  [1:0]	HOST_OPCODE;     
    input  [9:0]	HOST_ADDR;       
    input  [31:0]	HOST_WR_DATA;    
    input		HOST_REQ;        
    input		HOST_MIIM_SEL;   
    output [31:0]	HOST_RD_DATA;    
    output		HOST_MIIM_RDY;       

//*********************************Wire Declarations****************************

    // GMII transmit signals
    wire   [7:0]	gmii_txd_i;   
    wire 	        gmii_tx_en_i;   
    wire 	        gmii_tx_er_i;   

    // GMII receive signals
    wire   [7:0]	gmii_rxd_i;   
    wire 	        gmii_rx_dv_i;   
    wire 	        gmii_rx_er_i;   
    wire 	        gmii_rx_clk_i;

    // GMII control signals
    wire 	        gmii_col_i;   
    wire 	        gmii_crs_i;

    // Clock signal
    wire 	        tx_core_clk_i;

//*********************************Main Body of Code***************************

    //_____________________Instantiate GMAC Module_____________________________    
    GMAC gmac_inst	   
    (
	// Reset Signal
        .RESET(RESET),
        
        // Client Receiver Interface
        .RX_CLK(RX_CLK),
        .RX_GOOD_FRAME(RX_GOOD_FRAME),
        .RX_BAD_FRAME(RX_BAD_FRAME),
        .RX_DATA(RX_DATA),
        .RX_DATA_VALID(RX_DATA_VALID),
        .RX_STATISTICS_VECTOR(RX_STATISTICS_VECTOR),
        .RX_STATISTICS_VALID(RX_STATISTICS_VALID),
        
        // Client Transmitter Interface
        .TX_CLK(TX_CLK),
        .TX_DATA(TX_DATA),
        .TX_DATA_VALID(TX_DATA_VALID),
        .TX_UNDERRUN(TX_UNDERRUN),
        .TX_ACK(TX_ACK),
        .TX_RETRANSMIT(TX_RETRANSMIT),
        .TX_COLLISION(TX_COLLISION),
        .TX_IFG_DELAY(TX_IFG_DELAY),
        .TX_STATISTICS_VECTOR(TX_STATISTICS_VECTOR),
        .TX_STATISTICS_VALID(TX_STATISTICS_VALID),
        
        // MAC Control Interface
        .PAUSE_REQ(PAUSE_REQ),
        .PAUSE_VAL(PAUSE_VAL),
        
        // GMII Interface
        .GTX_CLK(tx_core_clk_i),
        .GMII_COL(gmii_col_i),
        .GMII_CRS(gmii_crs_i),
        .GMII_TXD(gmii_txd_i),
        .GMII_TX_EN(gmii_tx_en_i),
        .GMII_TX_ER(gmii_tx_er_i),
        .GMII_TX_CLK(GMII_TX_CLK),
        .GMII_RXD(gmii_rxd_i),
        .GMII_RX_DV(gmii_rx_dv_i),
        .GMII_RX_ER(gmii_rx_er_i),
        .GMII_RX_CLK(gmii_rx_clk_i),
        
        // MDIO Interface
        .MDIO_IN(MDIO_IN),   
        .MDIO_OUT(MDIO_OUT),
        .MDIO_TRI(MDIO_TRI),
        .MDC(MDC),
        
        // Host Interface
        .HOST_CLK(HOST_CLK),     
        .HOST_OPCODE(HOST_OPCODE),  
        .HOST_ADDR(HOST_ADDR),    
        .HOST_WR_DATA(HOST_WR_DATA), 
        .HOST_REQ(HOST_REQ),     
        .HOST_MIIM_SEL(HOST_MIIM_SEL),
        .HOST_RD_DATA(HOST_RD_DATA), 
        .HOST_MIIM_RDY(HOST_MIIM_RDY) 
    );
 
    //_____________________Instantiate RGMII Module____________________________  
    RGMII_GEN rgmii_shim
    (
        // Reset Signal 
        .RESET(RESET),
        
        // RGMII Interface
        .RGMII_TX_CTL_RISING(RGMII_TX_CTL_RISING),         
        .RGMII_TX_CTL_FALLING(RGMII_TX_CTL_FALLING),
        .RGMII_TXD_RISING(RGMII_TXD_RISING),
        .RGMII_TXD_FALLING(RGMII_TXD_FALLING),
        .RGMII_TX_CLK(RGMII_TX_CLK),
        .RGMII_RX_CTL_RISING (RGMII_RX_CTL_RISING),
        .RGMII_RX_CTL_FALLING(RGMII_RX_CTL_FALLING),
        .RGMII_RXD_RISING(RGMII_RXD_RISING),
        .RGMII_RXD_FALLING(RGMII_RXD_FALLING),
        .RGMII_RX_CLK(RGMII_RX_CLK),
        .RGMII_RX_SPEED(RGMII_RX_SPEED),
        .RGMII_RX_DUPLEX(RGMII_RX_DUPLEX),
        .RGMII_LINK(RGMII_LINK),
        
        // GMII Interface
        .GTX_CLK(GTX_CLK),
        .GMII_COL_TO_CORE(gmii_col_i),
        .GMII_CRS_TO_CORE(gmii_crs_i),
        .GMII_TXD_FROM_CORE(gmii_txd_i),
        .GMII_TX_EN_FROM_CORE(gmii_tx_en_i),
        .GMII_TX_ER_FROM_CORE(gmii_tx_er_i),
        .GMII_RXD_TO_CORE(gmii_rxd_i),
        .GMII_RX_DV_TO_CORE(gmii_rx_dv_i),
        .GMII_RX_ER_TO_CORE(gmii_rx_er_i),
         
        // CLK generator output 
        .TX_CORE_CLK(tx_core_clk_i),
        .RX_CORE_CLK(gmii_rx_clk_i)
    );

endmodule