ddr2_v340_ecc.v

基于SIIGX的PCIe的Kit

//Legal Notice: (C)2006 Altera Corporation. All rights reserved.  Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors.  Please refer to the applicable
//agreement for further details.

// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

//------------------------------------------------------------------------------
//*************** This is a MegaWizard generated file ****************
//Automatically generated example top level design to allow compilation
//of your DDR SDRAM Controller instance in Quartus.
//.
//This module instantiates your configured Altera DDR SDRAM Controller,
//some example driver logic, and a suitably configured PLL and DLL (where needed).
//.
//.
//Altera strongly recommends that you use this file as the starting point of your
//own project top level. This is because the IP Toolbench wizard parses this file
//to update parameters or generics, pin prefixes and other settings to match any
//changes you make in the wizard. The wizard will only update sections of code
//between its special tags so it is safe to edit this file and add your own logic
//to it. This is the recommended design flow for using the megacore.
//If you create your own top level or remove the tags, then you must make sure that
//any changes you make in the wizard are also applied to this file.
//Whilst editing this file make sure the edits are not inside any 'MEGAWIZARD'
//text insertion areas.
//(between <<START MEGAWIZARD INSERT and<<END MEGAWIZARD INSERT comments)
//Any edits inside these delimiters will be overwritten by the megawizard if you
//re-run it.
//If you really need to make changes inside these delimiters then delete
//both 'START' and 'END' delimiters.  This will stop the megawizard updating this
//section again.
//----------------------------------------------------------------------------------
//<< START MEGAWIZARD INSERT PARAMETER_LIST
//Parameters:
//Device Family                      : Stratix II
//local Interface Data Width         : 144
//DQ_PER_DQS                         : 8
//LOCAL_AVALON_IF                    : false
//MEM_CHIPSELS                       : 1
//MEM_CHIP_BITS                      : 0
//MEM_BANK_BITS                      : 2
//MEM_ROW_BITS                       : 13
//MEM_COL_BITS                       : 10
//LOCAL_BURST_LEN                    : 2
//LOCAL_BURST_LEN_BITS               : 2
//Number Of Output Clock Pairs       : 3
//<< END MEGAWIZARD INSERT PARAMETER_LIST
//----------------------------------------------------------------------------------
//<< MEGAWIZARD PARSE FILE DDR3.4.0
//.
//<< START MEGAWIZARD INSERT MODULE

module ddr2_v340_ecc (
                       // inputs:
                        clock_source,
                        reset_n,

                       // outputs:
                        clk_to_sdram_n,
                        clk_to_sdram_p,
                        ddr2_a,
                        ddr2_ba,
                        ddr2_cas_n,
                        ddr2_cke,
                        ddr2_cs_n,
                        ddr2_dm,
                        ddr2_dq,
                        ddr2_dqs,
                        ddr2_odt,
                        ddr2_ras_n,
                        ddr2_we_n,
                        pnf,
                        pnf_per_byte,
                        test_complete,

                        heartbeat
                     )
;

  output           heartbeat;
  reg     [25:0]   heartbeat_reg;

  always@(posedge clk)
     heartbeat_reg <= heartbeat_reg + 1;
  assign heartbeat = heartbeat_reg[25];

  output  [  2: 0] clk_to_sdram_n;
  output  [  2: 0] clk_to_sdram_p;
  output  [ 12: 0] ddr2_a;
  output  [  1: 0] ddr2_ba;
  output           ddr2_cas_n;
  output  [  0: 0] ddr2_cke;
  output  [  0: 0] ddr2_cs_n;
  output  [  8: 0] ddr2_dm;
  inout   [ 71: 0] ddr2_dq;
  inout   [  8: 0] ddr2_dqs;
  output  [  0: 0] ddr2_odt;
  output           ddr2_ras_n;
  output           ddr2_we_n;
  output           pnf;
  output  [ 17: 0] pnf_per_byte;
  output           test_complete;
  input            clock_source;
  input            reset_n;

  wire             clk;
  wire    [  2: 0] clk_to_sdram_n;
  wire    [  2: 0] clk_to_sdram_p;
  wire    [ 12: 0] ddr2_a;
  wire    [  1: 0] ddr2_ba;
  wire             ddr2_cas_n;
  wire    [  0: 0] ddr2_cke;
  wire    [  0: 0] ddr2_cs_n;
  wire    [  8: 0] ddr2_dm;
  wire    [ 71: 0] ddr2_dq;
  wire    [  8: 0] ddr2_dqs;
  wire    [ 23: 0] ddr2_local_addr;
  wire    [ 17: 0] ddr2_local_be;
  wire    [  9: 0] ddr2_local_col_addr;
  wire             ddr2_local_cs_addr;
  wire    [143: 0] ddr2_local_rdata;
  wire             ddr2_local_rdata_valid;
  wire             ddr2_local_read_req;
  wire             ddr2_local_ready;
  wire             ddr2_local_refresh_req;
  wire    [  1: 0] ddr2_local_size;
  wire    [143: 0] ddr2_local_wdata;
  wire             ddr2_local_wdata_req;
  wire             ddr2_local_write_req;
  wire    [  0: 0] ddr2_odt;
  wire             ddr2_ras_n;
  wire             ddr2_we_n;
  wire             dedicated_postamble_clk;
  wire             dedicated_resynch_or_capture_clk;
  wire    [  5: 0] dqs_delay_ctrl;
  wire             dqs_ref_clk;
  wire             dqsupdate;
  wire             pnf;
  wire    [ 17: 0] pnf_per_byte;
  wire             stratix_dll_control;
  wire             test_complete;
  wire             write_clk;
  //
 
  //
 
  //<< END MEGAWIZARD INSERT MODULE

  //<< START MEGAWIZARD INSERT REFRESH_REQ
  // Custom logic to implement user controlled refreshes can be added here....
  // refreshes disabled
  assign ddr2_local_refresh_req = 1'b0;

  //<< END MEGAWIZARD INSERT REFRESH_REQ

  //<< START MEGAWIZARD INSERT WRAPPER_NAME
  ddr2_topecc ddr2_topecc_ddr_sdram
    (
      .addrcmd_clk (clk),
      .clk (clk),
      .clk_to_sdram (clk_to_sdram_p[2 : 0]),
      .clk_to_sdram_n (clk_to_sdram_n[2 : 0]),
      .ddr2_a (ddr2_a),
      .ddr2_ba (ddr2_ba),
      .ddr2_cas_n (ddr2_cas_n),
      .ddr2_cke (ddr2_cke),
      .ddr2_cs_n (ddr2_cs_n),
      .ddr2_dm (ddr2_dm[8 : 0]),
      .ddr2_dq (ddr2_dq),
      .ddr2_dqs (ddr2_dqs[8 : 0]),
      .ddr2_odt (ddr2_odt),
      .ddr2_ras_n (ddr2_ras_n),
      .ddr2_we_n (ddr2_we_n),
      .dqs_delay_ctrl (dqs_delay_ctrl),
      .dqsupdate (dqsupdate),
      .local_addr (ddr2_local_addr),
      .local_be (ddr2_local_be),
      .local_init_done (),
      .local_rdata (ddr2_local_rdata),
      .local_rdata_valid (ddr2_local_rdata_valid),
      .local_rdvalid_in_n (),
      .local_read_req (ddr2_local_read_req),
      .local_ready (ddr2_local_ready),
      .local_refresh_ack (),
      .local_size (ddr2_local_size),
      .local_wdata (ddr2_local_wdata),
      .local_wdata_req (ddr2_local_wdata_req),
      .local_write_req (ddr2_local_write_req),
      .reset_n (reset_n),
      .resynch_clk (dedicated_resynch_or_capture_clk),
      .stratix_dll_control (stratix_dll_control),
      .write_clk (write_clk)
    );


  //<< END MEGAWIZARD INSERT WRAPPER_NAME

  //<< START MEGAWIZARD INSERT CS_ADDR_MAP
  //connect up the column address bits
  assign ddr2_local_addr[8 : 0] = ddr2_local_col_addr[9 : 1];

  //<< END MEGAWIZARD INSERT CS_ADDR_MAP

  //<< START MEGAWIZARD INSERT EXAMPLE_DRIVER
  //Self-test, synthesisable code to exercise the DDR SDRAM Controller
  ddr2_topecc_example_driver driver
    (
      .clk (clk),
      .local_bank_addr (ddr2_local_addr[23 : 22]),
      .local_be (ddr2_local_be),
      .local_col_addr (ddr2_local_col_addr),
      .local_cs_addr (ddr2_local_cs_addr),
      .local_rdata (ddr2_local_rdata),
      .local_rdata_valid (ddr2_local_rdata_valid),
      .local_read_req (ddr2_local_read_req),
      .local_ready (ddr2_local_ready),
      .local_row_addr (ddr2_local_addr[21 : 9]),
      .local_size (ddr2_local_size),
      .local_wdata (ddr2_local_wdata),
      .local_wdata_req (ddr2_local_wdata_req),
      .local_write_req (ddr2_local_write_req),
      .pnf_per_byte (pnf_per_byte),
      .pnf_persist (pnf),
      .reset_n (reset_n),
      .test_complete (test_complete)
    );


  //<< END MEGAWIZARD INSERT EXAMPLE_DRIVER

  //<< START MEGAWIZARD INSERT PLL
  ddr_pll_stratixii g_stratixpll_ddr_pll_inst
    (
      .c0 (clk),
      .c1 (write_clk),
      .c2 (dedicated_resynch_or_capture_clk),
      .c3 (dedicated_postamble_clk),
      .inclk0 (clock_source)
    );


  //<< END MEGAWIZARD INSERT PLL

  //<< START MEGAWIZARD INSERT DLL

  //------------------------------------------------------------
  //Instantiate Stratix Series DLL for Read DQS Phase shift
  //------------------------------------------------------------

  ddr2_topecc_auk_ddr_dll dll
    (
      .clk (dqs_ref_clk),
      .delayctrlout (dqs_delay_ctrl),
      .dqsupdate (dqsupdate),
      .reset_n (reset_n),
      .stratix_dll_control (stratix_dll_control)
    );


  //<< END MEGAWIZARD INSERT DLL

  //<< START MEGAWIZARD INSERT DQS_REF_CLK
  //---------------------------------------------------------------
  //DQS Reference clock connection for Stratix II
  //---------------------------------------------------------------

  assign dqs_ref_clk = clk;

  //<< END MEGAWIZARD INSERT DQS_REF_CLK

  //<< start europa

endmodule