rxinfofr.v

华大机顶盒源码

module RxInfoFr( CLKM, ResetN,
                 //input
                 bInfo, Fsync, Den, Rx_DB, Init_Mem_End, CompNewSeg_End, first_key,
                 //output
                 Init_Mem, RxNewSeg, Rx_SelLW,
                 Req_Mem, Mem_Blk_Num, Mem_Blk_Size,  Max_Seg_Num,
                 Seg_Num,
                 //debug
                 RxEn, DenCnt,dec_data
               );

input         CLKM;
input         ResetN;

input         bInfo;
input         Fsync;
input         Den;
input  [15:0] Rx_DB;
input         Init_Mem_End;
input         CompNewSeg_End;
input  [7:0]  first_key;

output        Init_Mem;
output        RxNewSeg;
output [7:0]  Req_Mem;
output [7:0]  Mem_Blk_Num;
output [15:0] Mem_Blk_Size;
output [11:0] Max_Seg_Num;
output [11:0] Seg_Num;
output        Rx_SelLW;

//debug
output [2:0]  DenCnt;
output        RxEn;
output [15:0] dec_data;

reg           Init_Mem;
reg           RxNewSeg;
reg           Rx_SelLW;
reg    [7:0]  Req_Mem;
reg    [7:0]  Mem_Blk_Num;
reg    [15:0] Mem_Blk_Size;
reg    [11:0]  Max_Seg_Num;
reg    [11:0]  Seg_Num;
reg           Start_Indicator;
reg    [2:0]  DenCnt;
reg    [4:0]  CurState;

reg    [7:0]  key;
reg           rst_key;
reg           set_key;

wire   [15:0]  dec_data;

wire RxEn;

assign RxEn = bInfo & Fsync & Den;
assign dec_data[15:8] = ~(key ^ ~Rx_DB[15:8]);
assign dec_data[7:0] = ~(Rx_DB[15:8] ^ ~Rx_DB[7:0]);

always @(posedge CLKM or negedge ResetN)
if(!ResetN) 
   key <= 0;
else if(rst_key)
   key <= first_key;
else if(set_key) 
   key <= Rx_DB[7:0];


parameter Idle = 5'b00001,
          RxHW1 = 5'b00010,
	  RxLW1 = 5'b00100,
	  RxLW2 = 5'b01000,
	  WaitNxtDen = 5'b10000;
	  
always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
	Init_Mem <= 0;
	RxNewSeg <= 0;
        Rx_SelLW <= 0;
	Req_Mem <= 0;
	Mem_Blk_Num <= 0;
	Mem_Blk_Size <= 0;
	Max_Seg_Num <= 0;
	Seg_Num <= 0;
	Start_Indicator <= 0;
	DenCnt <= 0;
	CurState <= Idle;
        rst_key <= 1;
        set_key <= 0;
end
else begin
	case (CurState)
		Idle : 
		begin
			if(Init_Mem_End)
				Init_Mem <= 0;
			if(CompNewSeg_End)
				RxNewSeg <= 0;
                        Rx_SelLW <= 0;
			Req_Mem <= Req_Mem;
			Mem_Blk_Num <= Mem_Blk_Num;
			Mem_Blk_Size <= Mem_Blk_Size;
			Max_Seg_Num <= Max_Seg_Num;
			Seg_Num <= Seg_Num;
			Start_Indicator <= 0;
			DenCnt <= 0;
                        set_key <= 0;
                       	rst_key <= 1;
			if(RxEn)
				CurState <= RxHW1;
		end
		RxHW1 : 
		begin
                        rst_key <= 0;
		        if (DenCnt != 3'b000)
		        	set_key <= 1;
		        else
		        	set_key <= 0;
		        	
			case (DenCnt)
			3'b000 : 
			begin
				Start_Indicator <= Rx_DB[6];
				CurState <= RxLW1;
			end
			3'b001 :
			begin
				if((dec_data[15:8]==8'hB7) && (dec_data[1]==1)) begin
//					DenCnt <= DenCnt + 1;
//					CurState <= WaitNxtDen;
                                        CurState <= RxLW1;
				end
				else 
					CurState <= Idle;
			end
			3'b010 : 
			begin
//				DenCnt <= DenCnt + 1;
//				CurState <= WaitNxtDen;
                                CurState <= RxLW1;
			end
			3'b011 : 
			begin
				if((dec_data[15:8]!=0) && (dec_data[7:0]==8'h44))
					CurState <= RxLW1;
				else
					CurState <= Idle;
			end
			3'b100 :
			begin
				if(!Init_Mem_End) begin
					if(dec_data[7]) begin
//						DenCnt <= DenCnt + 1;
//						CurState <= WaitNxtDen;
                                                CurState <= RxLW1;
					end
					else begin
						CurState <= Idle;
					end
				end
				else begin
					CurState <= RxLW1;
				end
			end
			3'b101 : 
			begin
				Req_Mem <= dec_data[7:0];
				CurState <= RxLW1;
			end
			3'b110 :
			begin
				Mem_Blk_Size[7:0] <= dec_data[15:8];
				Max_Seg_Num[11:4] <= dec_data[7:0];
                                CurState <= RxLW1;
//				Init_Mem <= 1;
//				CurState <= Idle;
			end
			default :
				CurState <= Idle;
			endcase	
		end
		RxLW1 :
		begin
			Rx_SelLW <= 1;
			CurState <= RxLW2;			
	        	set_key <= 0;
		end
		RxLW2 :
		begin
			Rx_SelLW <= 1;
		        if (DenCnt != 3'b000)
		        	set_key <= 1;
		        else
		        	set_key <= 0;

			case(DenCnt)
			3'b000 :
			begin
				if(Rx_DB[5:4]==2'b10) begin
					DenCnt <= DenCnt + 1;
					CurState <= WaitNxtDen;
				end
				else begin
					CurState <= Idle;
				end
			end
			3'b001 :
			begin
				DenCnt <= DenCnt + 1;
				CurState <= WaitNxtDen;
			end
			3'b010 : 
			begin
				DenCnt <= DenCnt + 1;
				CurState <= WaitNxtDen;
			end
			3'b011 : 
			begin
				if(dec_data[15:8]==8'h5A) begin
					DenCnt <= DenCnt + 1;
					CurState <= WaitNxtDen;
				end
				else
					CurState <= Idle;
			end
			3'b100 : 
			begin
				if(!Init_Mem_End) begin
					DenCnt <= DenCnt + 1;
					CurState <= WaitNxtDen;
				end
				else begin	
					Seg_Num <= dec_data[11:0];
					if(Start_Indicator)
						RxNewSeg <= 1;
					else if(Seg_Num != dec_data[11:0])
						RxNewSeg <= 1;
					else
						RxNewSeg <= 0;
					CurState <= Idle;				
				end
			end
			3'b101 : 
			begin
				Mem_Blk_Num <= dec_data[15:8];
				Mem_Blk_Size[15:8] <= dec_data[7:0];
				DenCnt <= DenCnt + 1;
				CurState <= WaitNxtDen;
			end
			3'b110 :
			begin
				Max_Seg_Num[3:0] <= dec_data[15:12];
				Init_Mem <= 1;
				CurState <= Idle;
			end
			default :
				CurState <= Idle;
			endcase
		end
		WaitNxtDen :
		begin
			Rx_SelLW <= 0;
	        	set_key <= 0;
			if(Den)
				CurState <= RxHW1;
			else
				CurState <= WaitNxtDen;
		end
		default :
			CurState <= Idle;
	endcase
end

endmodule