pctofpga.v

這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder

`include "Datapath.v"
`include "Controlpath.v"
`include "Chang3to2.v"
module PcToFPGA(
		Clk,			//Clock
		Reset,			//Reset State
		Control_R_W,		//Con_R_W = 1 ==> PC to FPGA,
					//Con_R_W = 0 ==> FPGA to PC.
		PC_Check_1,
		PC_Check_2,
		FPGA_Check,
		
		Sel,			//Sel[0] ==> 0 ==> Mamery Address(A,B) ==>Counter_Out
		    			//Sel[0] ==> 1 ==> Mamery Address(A,B) ==>DWT_Memory_(A,B)_Address
		    			//Sel[1] ==> 0 ==> bidirec(inp) <== Memory_Out_Data(A)
		    			//Sel[1] ==> 1 ==> bidirec(inp) <== Memory_Out_Data(B)

		OutData_Memory_A,	//Memory_A_Data out
		We_Memory_A,
		Address_Memory_A,
		InData_Memory_A,
		
		OutData_Memory_B,	//Memory_A_Data out
		We_Memory_B,
		Address_Memory_B,
		InData_Memory_B,
		
//		Out_Counter_128bits,
		Done_Counter_128bits,

		bidir
		);                                                                   

parameter Data_Width = 20;	//Data Width
parameter Address_Width = 12;	//Address Width 12bits = 4096
parameter OutData_Width = 8;	//Output Data Width

input	Clk;                 
input	Reset;
input	Control_R_W;
input	PC_Check_1;
input	PC_Check_2;
output	FPGA_Check;


input	[2:0]	Sel;

output	[Data_Width-1:0]	OutData_Memory_A;	//Memory_A_Data out
input				We_Memory_A;
input	[Address_Width-1:0]	Address_Memory_A;
input	[Data_Width-1:0]	InData_Memory_A;

output	[Data_Width-1:0]	OutData_Memory_B;	//Memory_A_Data out
input				We_Memory_B;
input	[Address_Width-1:0]	Address_Memory_B;
input	[Data_Width-1:0]	InData_Memory_B;

output				Done_Counter_128bits;
                     
inout	[OutData_Width-1:0]	bidir;
		                                                                   
wire	Temp1;
wire	Temp2;
wire	Temp3;

wire	Temp4;
wire	Temp5;
wire	Temp6;

Chang3to2	Chang(                                                       
		.In_Signal_A(We_Memory_A),	//DWT control We_A               
		.In_Signal_B(We_Memory_B),	//DWT control We_B               
		.Control_Signal(Temp3),		//transform control We_A or We_B 
		                                                         
		.Sel(Sel[2:1]),				//Select                         
		.Out_Signal_A(Temp_We_Memory_A),	//Out_We_A                       
		.Out_Signal_B(Temp_We_Memory_B)	//Out_We_B                       
		);                                                       




ControlPath	A1(
		.Clk(Clk),			//Clock
		.Reset(Reset),			//Clear Control Path State
		.Control_R_W(Control_R_W),	//Control_R_W = 0 ==> FPGA to PC,
						//Control_R_W = 1 ==> PC to FPGA,
		.PC_Check_1(PC_Check_1),	//PC_Check_1  = 1 ==> PC to FPGA, Data OK.
		.PC_Check_2(PC_Check_2),	//PC_Check_2  = 1 ==> PC check FPGA signal.
		.FPGA_Check(FPGA_Check),	//FPGA_Check  = 1 ==> Write in memory.

		.Reset_Count128(Temp1),			//Reset_Counter128 = 0 ==> Clear Counter128
		.Wen_Count128(Temp2),			//Wen_Counter128   = 1 ==> Count++
		.Done_Count128(Done_Counter_128bits),	//Count == END 	       ==> Done_Count128 = 1
		  	
		.Reset_Count_State(Temp5),	//Reset_Count_State = 0 ==> clear Count
		.Wen_Count_State(Temp4),	//Wen_Count_State   = 1 ==> Count++
		.Done_Count_State(Temp6),	//Count == END 	        ==> Done_Count_State = 1
                
	   	.Wen_Memory(Temp3)	//Write In Memory
	   	);

DataPath	B1(
		.Clk(Clk),			//Clock
		.Sel(Sel[1:0]),			//Sel[0] ==> 0 ==> Mamery Address(A,B) ==>Counter_Out
						//Sel[0] ==> 1 ==> Mamery Address(A,B) ==>DWT_Memory_(A,B)_Address
						//Sel[1] ==> 0 ==> bidirec(inp) <== Memory_Out_Data(A)
						//Sel[1] ==> 1 ==> bidirec(inp) <== Memory_Out_Data(B)
                .We_Memory_A(Temp_We_Memory_A),	//[0:0]
                .Q_Memory_A_OutData(OutData_Memory_A),	//[7:0]

                .We_Memory_B(Temp_We_Memory_B),		//[0:0]
                .Q_Memory_B_OutData(OutData_Memory_B),	//[7:0]

                .Wen_Counter_128bits(Temp2),	//[0:0]
                .Reset_Counter_128bits(Temp1),	//[0:0]
                .Done_Counter_128bits(Done_Counter_128bits),	//[0:0]

                .Wen_Counter_State(Temp4),	//[0:0]	
                .Reset_Counter_State(Temp5),	//[0:0]
                .Done_Counter_State(Temp6),	//[0:0]

                .DWT_Memory_A_Address(Address_Memory_A),	//[13:0]
                .DWT_Memory_B_Address(Address_Memory_B),	//[13:0]
                .DWT_Memory_A_InData(InData_Memory_A),	//[7:0]
                .DWT_Memory_B_InData(InData_Memory_B),	//[7:0]

                .Oe_Bidirec(!Control_R_W),		//[0:0]
                .bidir(bidir)			//[7:0]
                );
endmodule