📄 controlpath.v
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module ControlPath(
Clk, //Clock
Reset, //Clear Control Path State
Control_R_W, //Control_R_W = 0 ==> FPGA to PC,
//Control_R_W = 1 ==> PC to FPGA,
PC_Check_1, //PC_Check_1 = 1 ==> PC to FPGA, Data OK.
PC_Check_2, //PC_Check_2 = 1 ==> PC check FPGA signal.
FPGA_Check, //FPGA_Check = 1 ==> Write in memory.
Reset_Count128, //Reset_Counter128 = 0 ==> Clear Counter128
Wen_Count128, //Wen_Counter128 = 1 ==> Count++
Done_Count128, //Count == END ==> Done_Count128 = 1
Reset_Count_State, //Reset_Count_State = 0 ==> clear Count
Wen_Count_State, //Wen_Count_State = 1 ==> Count++
Done_Count_State, //Count == END ==> Done_Count_State = 1
Wen_Memory //Write In Memory
);
input Clk; //Clock
input Reset; //Clear Control Path State
input Control_R_W; //Control_R_W = 0 ==> FPGA to PC,
//Control_R_W = 1 ==> PC to FPGA,
input PC_Check_1; //PC_Check_1 = 1 ==> PC to FPGA, Data OK.
input PC_Check_2; //PC_Check_2 = 1 ==> PC check FPGA signal.
output FPGA_Check; //FPGA_Check = 1 ==> Write in memory.
output Reset_Count128; //Reset_Counter128 = 0 ==> Clear Counter128
output Wen_Count128; //Wen_Counter128 = 1 ==> Count++
input Done_Count128; //Count == END ==> Done_Count128 = 1
output Reset_Count_State; //Reset_Count_State = 0 ==> clear Count
output Wen_Count_State; //Wen_Count_State = 1 ==> Count++
input Done_Count_State; //Count == END ==> Done_Count_State = 1
output Wen_Memory; //Write In Memory
//========== State ==========
reg [3:0] CurrentState;
reg [3:0] NextState;
//===========================
//========== reg ==========
reg FPGA_Check;
reg Reset_Count128;
reg Wen_Count128;
reg Reset_Count_State;
reg Wen_Count_State;
reg Wen_Memory;
//=========================
//================================================================================================================================
parameter [3:0] Start = 4'b0000,
PC_to_FPGA_1 = 4'b0001, //Wait PC_Check_1 = 1
PC_to_FPGA_2 = 4'b0010, //Wen_Memory = 1, Write In Memory
PC_to_FPGA_3 = 4'b0011, //Count++
PC_to_FPGA_4 = 4'b0100, //Wait PC_Check_1 = 1, PC_Check_2 = 1, ==> (True) FPGA_Check = 1, (False) FPGA_Check = 0.
PC_to_FPGA_5 = 4'b0101, //Wait PC_Check_1 = 0, PC_Check_2 = 0, ==> (True) To PC_to_FPGA_1, (False) PC_to_FPGA_5
PC_to_FPGA_6 = 4'b0110, //END, Count = END, Done_Count128 = 1
PC_to_FPGA_7 = 4'b0111; //Wait Delay
//================================================================================================================================
parameter [3:0] FPGA_to_PC_1 = 4'b0001, //Wait Done_Count_State == 1, (True) FPGA_to_PC_2, (False) FPGA_to_PC_1
FPGA_to_PC_2 = 4'b0010, //Wait Done_Count128 == 0, (True) FPGA_to_PC_3, (False) FPGA_to_PC_2
FPGA_to_PC_3 = 4'b0011, //Wait PC_Check_1 == 1, (True) FPGA_to_PC_4, FPGA_Check = 1, (False) FPGA_to_PC_3, FPGA_Check = 0
FPGA_to_PC_4 = 4'b0100, //Wait PC_Check_1 & PC_Check_2 == 1, FPGA_Check = 1, (True) FPGA_to_PC_5, (False) FPGA_to_PC_4
FPGA_to_PC_5 = 4'b0101, //Count++, FPGA_Check = 0
FPGA_to_PC_6 = 4'b0110, //Wait PC_Check_1 & PC_Check_2 = 0, FPGA = 0, (True) FPGA_to_PC_2, (False) FPGA_to_PC_6
FPGA_to_PC_7 = 4'b0111; //Wait Delay
//================================================================================================================================
//====================
//===== Sequence =====
//====================
always @(posedge Clk)
begin
if(!Reset)
CurrentState = Start;
else
CurrentState = NextState;
end
//==========================
//===== Sequence State =====
//==========================
always @(CurrentState or Control_R_W)
begin
case({Control_R_W,CurrentState})
//===========================================
//===== Control_R_W = 1, ==> PC to FPGA =====
//===========================================
5'b1_0000:begin //Start = 0
if(!Reset)
NextState = Start;
else
NextState = PC_to_FPGA_1;
end
5'b1_0001:begin //PC_to_FPGA_1 = 1
// if(Done_Count128)
// NextState = PC_to_FPGA_6; //To END
if(PC_Check_1)
NextState = PC_to_FPGA_2; //Done_Count128 = 0, PC_Check_1 = 1
else
NextState = PC_to_FPGA_1; //Done_Count128 = 0, PC_Check_1 = 0
end
5'b1_0010:begin //PC_to_FPGA_2 = 2
if(!Done_Count_State)
NextState = PC_to_FPGA_2;
else
NextState = PC_to_FPGA_3; //Write is OK.
end
5'b1_0011:begin //PC_to_FPGA_3 = 3
NextState = PC_to_FPGA_4; //Count++
end
5'b1_0100:begin //PC_to_FPGA_4 = 4
if(PC_Check_2 == 1)
NextState = PC_to_FPGA_5; //Wait PC_Check_1 = PC_Check_2 = 1
else
NextState = PC_to_FPGA_4;
end
5'b1_0101:begin //PC_to_FPGA_5 = 5
if(PC_Check_1 == 0 && PC_Check_2 == 0)
NextState = PC_to_FPGA_7; //Wait PC_Check_1 = PC_Check_2 = 0
else
NextState = PC_to_FPGA_5;
end
5'b1_0110:begin //PC_to_FPGA_6 = 6
NextState = PC_to_FPGA_6;
end
5'b1_0111:begin //PC_to_FPGA_7 = 7
if(Done_Count_State)
NextState = PC_to_FPGA_1;
else
NextState = PC_to_FPGA_7;
end
//===========================================
//===== Control_R_W = 0, ==> FPGA to PC =====
/*
FPGA_to_PC_1 = 4'b0001; //Wait Done_Count_State == 1, (True) FPGA_to_PC_2, (False) FPGA_to_PC_1
FPGA_to_PC_2 = 4'b0010; //Wait Done_Count128 == 0, (True) FPGA_to_PC_3, (False) FPGA_to_PC_2
FPGA_to_PC_3 = 4'b0011; //Wait PC_Check_1 == 1, (True) FPGA_to_PC_4, FPGA_Check = 1, (False) FPGA_to_PC_3, FPGA_Check = 0
FPGA_to_PC_4 = 4'b0100; //Wait PC_Check_1 & PC_Check_2 == 1, FPGA_Check = 1, (True) FPGA_to_PC_5, (False) FPGA_to_PC_4
FPGA_to_PC_5 = 4'b0101; //Count++, FPGA_Check = 0
FPGA_to_PC_6 = 4'b0110; //Wait PC_Check_1 & PC_Check_2 = 0, FPGA = 0, (True) FPGA_to_PC_2, (False) FPGA_to_PC_6
*/
//===========================================
5'b0_0000:begin //Start = 0
if(!Reset)
NextState = Start;
else
NextState = FPGA_to_PC_1; //Wait Reset = 1
end
5'b0_0001:begin //FPGA_to_PC_1 = 1
if(!Done_Count_State)
NextState = FPGA_to_PC_1;
else
NextState = FPGA_to_PC_2; //Wait Done_Count_State = 1
end
5'b0_0010:begin //FPGA_to_PC_2 = 2
if(Done_Count128) //Wait Done_Count128
NextState = FPGA_to_PC_2; //if(Done_Count128) FPGA_Check = 0
else
NextState = FPGA_to_PC_3; //if(!Done_Count128) FPGA_Check = 0
end
5'b0_0011:begin //FPGA_to_PC_3 = 3
if(PC_Check_1) //Wait PC_Check_1 == 1
NextState = FPGA_to_PC_7;
else
NextState = FPGA_to_PC_3;
end
5'b0_0100:begin //FPGA_to_PC_4 = 4
if(PC_Check_2)
NextState = FPGA_to_PC_5;
else
NextState = FPGA_to_PC_4;
end
5'b0_0101:begin //FPGA_to_PC_5 = 5
NextState = FPGA_to_PC_6;
end
5'b0_0111:begin //FPGA_to_PC_5 = 7
if(Done_Count_State)
NextState = FPGA_to_PC_4;
else
NextState = FPGA_to_PC_7;
end
5'b0_0110:begin //FPGA_to_PC_6 = 6
if(PC_Check_1 == 0 && PC_Check_2 == 0)
NextState = FPGA_to_PC_2;
else
NextState = FPGA_to_PC_6;
end
default:NextState = Start;
endcase
end
//===========================
//===== Sequence Output =====
//===========================
always @(CurrentState)
begin
case({Control_R_W,CurrentState})
//===========================================
//===== Control_R_W = 1, ==> PC to FPGA =====
//===========================================
5'b1_0000:begin //Start = 0
FPGA_Check = 0;
Reset_Count128 = 0;
Wen_Count128 = 0;
Reset_Count_State = 0;
Wen_Count_State = 0;
Wen_Memory = 0;
end
5'b1_0001:begin //PC_to_FPGA_1 = 1
FPGA_Check = 0;
Reset_Count128 = 1;
Wen_Count128 = 0;
Reset_Count_State = 0;
Wen_Count_State = 0;
Wen_Memory = 0;
end
5'b1_0010:begin //PC_to_FPGA_2 = 2
FPGA_Check = 0;
Reset_Count128 = 1;
Wen_Count128 = 0;
Reset_Count_State = 1;
Wen_Count_State = 1;
Wen_Memory = 1;
end
5'b1_0011:begin //PC_to_FPGA_3 = 3
FPGA_Check = 1; //Count++, FPGA_Check = 1
Reset_Count128 = 1;
Wen_Count128 = 1;
Reset_Count_State = 0;
Wen_Count_State = 0;
Wen_Memory = 0;
end
5'b1_0100:begin //PC_to_FPGA_4 = 4
FPGA_Check = 1;
Reset_Count128 = 1;
Wen_Count128 = 0;
Reset_Count_State = 0;
Wen_Count_State = 0;
Wen_Memory = 0;
end
5'b1_0101:begin //PC_to_FPGA_5 = 5
FPGA_Check = 0;
Reset_Count128 = 1;
Wen_Count128 = 0;
Reset_Count_State = 0;
Wen_Count_State = 0;
Wen_Memory = 0;
end
5'b1_0110:begin //PC_to_FPGA_6 = 6
FPGA_Check = 0;
Reset_Count128 = 1;
Wen_Count128 = 0;
Reset_Count_State = 0;
Wen_Count_State = 0;
Wen_Memory = 0;
end
5'b1_0111:begin //PC_to_FPGA_7 = 7
FPGA_Check = 0;
Reset_Count128 = 1;
Wen_Count128 = 0;
Reset_Count_State = 1;
Wen_Count_State = 1;
Wen_Memory = 0;
end
//===========================================
//===== Control_R_W = 0, ==> FPGA to PC =====
//===========================================
5'b0_0000:begin //Start = 0
FPGA_Check = 0;
Reset_Count128 = 0;
Wen_Count128 = 0;
Reset_Count_State = 0;
Wen_Count_State = 0;
Wen_Memory = 0;
end
5'b0_0001:begin //FPGA_to_PC_1 = 1
FPGA_Check = 0;
Reset_Count128 = 1;
Wen_Count128 = 0;
Reset_Count_State = 1;
Wen_Count_State = 1;
Wen_Memory = 0;
end
5'b0_0010:begin //FPGA_to_PC_2 = 2
FPGA_Check = 0;
Reset_Count128 = 1;
Wen_Count128 = 0;
Reset_Count_State = 0;
Wen_Count_State = 0;
Wen_Memory = 0;
end
5'b0_0011:begin //FPGA_to_PC_3 = 3
FPGA_Check = 0;
Reset_Count128 = 1;
Wen_Count128 = 0;
Reset_Count_State = 0;
Wen_Count_State = 0;
Wen_Memory = 0;
end
5'b0_0100:begin //FPGA_to_PC_4 = 4
FPGA_Check = 1;
Reset_Count128 = 1;
Wen_Count128 = 0;
Reset_Count_State = 0;
Wen_Count_State = 0;
Wen_Memory = 0;
end
5'b0_0101:begin //FPGA_to_PC_5 = 5
FPGA_Check = 0;
Reset_Count128 = 1;
Wen_Count128 = 1;
Reset_Count_State = 0;
Wen_Count_State = 0;
Wen_Memory = 0;
end
5'b0_0110:begin //FPGA_to_PC_6 = 6
FPGA_Check = 0;
Reset_Count128 = 1;
Wen_Count128 = 0;
Reset_Count_State = 0;
Wen_Count_State = 0;
Wen_Memory = 0;
end
5'b0_0111:begin //FPGA_to_PC_5 = 7
FPGA_Check = 0;
Reset_Count128 = 1;
Wen_Count128 = 0;
Reset_Count_State = 1;
Wen_Count_State = 1;
Wen_Memory = 0;
end
default:begin
FPGA_Check = 0;
Reset_Count128 = 1;
Wen_Count128 = 0;
Reset_Count_State = 0;
Wen_Count_State = 0;
Wen_Memory = 0;
end
endcase
end
endmodule⌨️ 快捷键说明
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