cputop2.v

verilog语言写的简单八位处理器。有8个模块

`include"ram.v"
`include"rom.v"
`include"addr_decode.v"
`include"cpu.v"
 

`timescale 1ns/100ps
`define PERIOD 100
module cputop;

reg reset_req,CLOCK;
integer test;
reg[(3*8):0]mnemonic;
reg[12:0] PC_ADDR,IR_ADDR;
wire[7:0]DATA;
wire[12:0]ADDR;
wire RD,WR,HALT,ram_sel,rom_sel;



cpu t_cpu(.CLK(CLOCK),.RESET(reset_req),.HALT(HALT),.RD(RD),.WR(WR),.ADDR(ADDR),.DATA(DATA));
ram t_ram (.ADDR(ADDR[9:0]),.READ(RD),.WRITE(WR),.ENA(ram_sel),.DATA(DATA));
rom t_rom(.ADDR(ADDR),.READ(RD),.ENA(rom_sel),.DATA(DATA));
addr_decode  t_addr_decode(.ADDR(ADDR),.ram_sel(ram_sel),.rom_sel(rom_sel));


initial  
	begin
    	CLOCK=1;
	reset=0;
	t_rom[0]=00000001;
	t_rom[1]=00000000;
	t_rom[2]=00000000;
	t_rom[3]=10010000;


	t_ram[0]=101_11000;
	t_ram[1]=0000_0000;
	t_ram[2]=110_11000;
	t_ram[3]=0000_0010;
	t_ram[4]=010_11000;
	t_ram[5]=0000_0000;
	t_ram[6]=110_11000;
	t_ram[7]=0000_0001;
	t_ram[8]=101_11000;
	t_ram[9]=0000_0010;
	t_ram[10]=110_11000;
	t_ram[11]=0000_0000;
	t_ram[12]=100_11000;
	t_ram[13]=0000_0011;
	t_ram[14]=001_00000;
	t_ram[15]=0000_0000;
	t_ram[16]=111_00000;
	t_ram[17]=0000_0000;
	t_ram[18]=0000_0000;
	t_ram[19]=0000_0000;
	
 	
	#50 reset=1;
	#100000 $stop;
	end
	always #50 clock=~clock;
endmodule