ram.v

来自「verilog语言写的简单八位处理器。有8个模块」· Verilog 代码 · 共 12 行

module ram(DATA,ADDR,ENA,READ,WRITE);
    inout[7:0] DATA;
    input [9:0] ADDR;
    input ENA;
    input READ,WRITE;
    reg[7:0] ram[10'h3ff:0];
    assign DATA=(READ&&ENA)? ram[ADDR]:8'hzz;
    always@(posedge WRITE)
    begin
        ram[ADDR]<=DATA;
    end
endmodule