addr_decode.v

来自「verilog语言写的简单八位处理器。有8个模块」· Verilog 代码 · 共 15 行

module addr_decode(ADDR,rom_sel,ram_sel);
    output rom_sel,ram_sel;
    input [12:0] ADDR;
    reg rom_sel,ram_sel;
    always@(ADDR)
    begin
        casex(ADDR)
            13'b1_1xxx_xxxx_xxxx:{rom_sel,ram_sel}<=2'b01;
            13'b0_xxxx_xxxx_xxxx:{rom_sel,ram_sel}<=2'b10;
            13'b1_0xxx_xxxx_xxxx:{rom_sel,ram_sel}<=2'b10;
            default :{rom_sel,ram_sel}<=2'b00;
        endcase
    end
endmodule