register.v

来自「verilog语言写的简单八位处理器。有8个模块」· Verilog 代码 · 共 38 行

module register(OPC_IRADDR,DATA,ENA,CLK1,RESET);
    output[15:0] OPC_IRADDR;
    input[7:0] DATA;
    input ENA,CLK1,RESET;
    reg [15:0] OPC_IRADDR;
    reg state;
    always@(posedge CLK1)
    begin
        if(RESET)
           begin
               OPC_IRADDR<=16'b0000_0000_0000_0000;
               state<=1'b0;
           end
        else
           begin
               if(ENA)
               begin
                   casex(state)
                       1'b0:begin
                           OPC_IRADDR[15:8]<=DATA;
                           state<=1;
                             end
                        1'b1:begin
                            OPC_IRADDR[7:0]<=DATA;
                            state<=0;
                              end
                    default: begin
                                  OPC_IRADDR[15:0]<=16'bxxxxxxxxxxxxxxxx;
                                   state<=1'bx;
                            end
                    endcase
                end
            else
                state<=1'b0;
            end
        end
endmodule