alu.v

来自「verilog语言写的简单八位处理器。有8个模块」· Verilog 代码 · 共 35 行

module alu(ALU_OUT,ZERO,DATA,ACCUM,ALU_CLK,OPCODE);
   output[7:0]ALU_OUT;
   output ZERO;
   input[7:0]DATA,ACCUM;
   input[2:0]OPCODE;
   input ALU_CLK;
   reg[7:0]ALU_OUT;
    parameter HLT=3'b000,
               SKZ=3'b001,
                ADD=3'b010,
                ANDD=3'b011,
                XORR=3'b100,
                LDA=3'b101,
                STO=3'b110,
                JMP=3'b111;
    assign ZERO=!ACCUM;
    always@(posedge ALU_CLK)
       begin
           casex(OPCODE)
                HLT:ALU_OUT<=ACCUM;
               SKZ:ALU_OUT<=ACCUM;
                ADD:ALU_OUT<=DATA+ACCUM;
                ANDD:ALU_OUT<=DATA&ACCUM;
                XORR:ALU_OUT<=DATA^ACCUM;
                LDA:ALU_OUT<=DATA;
                STO:ALU_OUT<=ACCUM;
                JMP:ALU_OUT<=ACCUM;
                default:ALU_OUT<=8'bxxxx_xxxx;
        endcase
    end
endmodule