accum.v

verilog语言写的简单八位处理器。有8个模块

module accum(ACCUM,DATA,ENA,CLK1,RST);
    output[7:0]ACCUM;
    input[7:0]DATA;
    input ENA,CLK1,RST;
    reg[7:0]ACCUM;
    
    always@(posedge CLK1)
       begin
        if(RST)
           ACCUM<=8'b0000_0000;
        else
           if(ENA)
              ACCUM<=DATA;
    end
    
endmodule