cpu.v

verilog语言写的简单八位处理器。有8个模块

//`include "clk_gen.v"
//`include "accum.v"
//`include "adr.v"
//`include "alu.v"
//`include "machine.v"
//`include "counter.v"
//`include "machinectl.v"
//`include "register.v"
//`include "datact1.v"
module cpu(CLK,RESET,HALT,RD,WR,ADDR,DATA);
    input CLK,RESET;
    output RD,WR,ADDR,HALT;
    inout DATA;
    wire CLK,RESET,HALT;
    wire[7:0] DATA;
    wire[12:0] ADDR;
    wire RD,WR;
    wire CLK1,FETCH,ALU_CLK;
    wire [2:0] OPCODE;
    wire[12:0]IR_ADDR,PC_ADDR;
    wire[7:0]ALU_OUT,ACCUM;
    wire ZERO,INC_PC,LOAD_ACC,LOAD_PC,LOAD_IR,DATA_ENA,CONTR_ENA;
    clk_gen m_clk_gen(.CLK(CLK),.CLK1(CLK1),.FETCH(FETCH),.ALU_CLK(ALU_CLK),.RESET(RESET));
    register m_register(.DATA(DATA),.ENA(LOAD_IR),.RST(RESET),.CLK1(CLK1),.OPC_IRADDR({OPCODE,IR_ADDR}));
    accum m_accum (.DATA(ALU.OUT),.ENA(LOAD_ACC),.CLK1(CLK1),.RESET(RESET),.ACCUM(accum));
    alu m_alu (.data(data),.ACCUM(accum),.alu_clk(alu_clk),.opcode(opcode),.alu_out(alu_out),.zero(zero));
    machinectl m_machinectl(.ena(contr_ena),.fetch(fetch),.rst(reset));
    
    machine m_machine (.inc_pc(inc_pc),.load_acc(load_acc),.load_pc(load_pc),
                      .rd(rd),.wr(wr),.load_ir(load_ir),.clk1(clk1),
                       .datactl_ena(data_ena),.halt(halt),.zero(zero),
                       .ena(contr_ena),.opcode(opcode));
    datactl m_datactl (.in(alu_out),.data_ena(data_ena),.data(data));
    adr m_adr (.fetch(fetch),.ir_addr(ir_addr),.pc_addr(pc_addr),.addr(addr));
    counter m_counter(.ir_addr(ir_addr),.load(load_pc),.clock(inc_pc),.rst(reset),.pc_addr(pc_addr));
endmodule