machine.v

verilog语言写的简单八位处理器。有8个模块

module machine(INC_PC,LOAD_ACC,LOAD_PC,RD,WR,LOAD_IR,
                        DATACTL_ENA,HALT,CLK1,ZERO,ENA,OPCODE);
         output INC_PC, LOAD_ACC,LOAD_PC,RD,WR,LOAD_IR;
         output DATACTL_ENA,HALT;
         input CLK1,ZERO,ENA;
         input[3:0] OPCODE;
         reg INC_PC,LOAD_ACC,LOAD_PC,RD,WR,LOAD_IR;
         reg DATACTL_ENA,HALT;
         reg[2:0] state;
         parameter HLT=4'b0000,
                   SKZ=4'b0001,
                   ADD=4'b0010,
                   ANDD=4'b0011,
                   XORR=4'b0100,
                   LDA=4'b0101,
                   STO=4'b0110,
                   JMP=4'b0111;
        always@(negedge CLK1)
        begin 
        if(!ENA)
           begin
               state<=4'b0000;
               {INC_PC,LOAD_ACC,LOAD_PC,RD}<=4'b0000;
               {WR,LOAD_IR,DATACTL_ENA,HALT}<=4'b0000;
           end
        else
           ctl_cycle;
       end
//.....................begin of task ctl_cycle................
task ctl_cycle;
    begin
        casex(state)
            4'b0000:
               begin
                   {INC_PC,LOAD_ACC,LOAD_PC,RD}<=4'b0001;
                   {WR,LOAD_IR,DATACTL_ENA,HALT}<=4'b0100;
                   state<=4'b0001;
               end
            4'b0001:
               begin
                   {INC_PC,LOAD_ACC,LOAD_PC,RD}<=4'b1001;
                   {WR,LOAD_IR,DATACTL_ENA,HALT}<=4'b0100;
                   state<=4'b0010;
               end
            4'b0010:
               begin
                   {INC_PC,LOAD_ACC,LOAD_PC,RD}<=4'b0000;
                   {WR,LOAD_IR,DATACTL_ENA,HALT}<=4'b0000;
                    state<=4'b0011;
               end
            4'b0011:
               begin
                  if(OPCODE==HLT)
                  begin
                  {INC_PC,LOAD_ACC,LOAD_PC,RD}<=4'b1000;
                  {WR,LOAD_IR,DATACTL_ENA,HALT}<=4'b0001;
                   end 
                   else
                   begin
                       {INC_PC,LOAD_ACC,LOAD_PC,RD}<=4'b1000;
                       {WR,LOAD_IR,DATACTL_ENA,HALT}<=4'b0000;
                   end
                   state<=4'b0100;
               end
            4'b0100:
                  begin
                   if(OPCODE==JMP)
                      begin
                          {INC_PC,LOAD_ACC,LOAD_PC,RD}<=4'b0010;
                          {WR,LOAD_IR,DATACTL_ENA,HALT}<=4'b0000;
                      end
                      else
                         if(OPCODE==ADD||OPCODE==ANDD||OPCODE==XORR||OPCODE==LDA)
                         begin
                          {INC_PC,LOAD_ACC,LOAD_PC,RD}<=4'b0001;
                          {WR,LOAD_IR,DATACTL_ENA,HALT}<=4'b0000;
                          end
                      else
                         if(OPCODE==STO)
                           begin
                           {INC_PC,LOAD_ACC,LOAD_PC,RD}<=4'b0000;
                           {WR,LOAD_IR,DATACTL_ENA,HALT}<=4'b0010;
                           end
                       else
                          begin
                              {INC_PC,LOAD_ACC,LOAD_PC,RD}<=4'b0000;
                              {WR,LOAD_IR,DATACTL_ENA,HALT}<=4'b0000;
                          end
                          state<=4'b0101;
                  end
4'b0101:
         begin
             if(OPCODE==ADD||OPCODE==ANDD||OPCODE==XORR||OPCODE==LDA)
                begin
                    {INC_PC,LOAD_ACC,LOAD_PC,RD}<=4'b1000;
                    {WR,LOAD_IR,DATACTL_ENA,HALT}<=4'b0000;
                end
             else
               if(OPCODE==SKZ&&ZERO==1)
                 begin
                     {INC_PC,LOAD_ACC,LOAD_PC,RD}<=4'b1000;
                     {WR,LOAD_IR,DATACTL_ENA,HALT}<=4'b0000;
                 end
                else
                    if(OPCODE==JMP)
                       begin
                        {INC_PC,LOAD_ACC,LOAD_PC,RD}<=4'b1010;
                        {WR,LOAD_IR,DATACTL_ENA,HALT}<=4'b0000;
                       end
                    else
                        if(OPCODE==STO)
                           begin
                           {INC_PC,LOAD_ACC,LOAD_PC,RD}<=4'b0000;
                           {WR,LOAD_IR,DATACTL_ENA,HALT}<=4'b1010;
                           end                    
                        else
                            begin
                                {INC_PC,LOAD_ACC,LOAD_PC,RD}<=4'b0000;
                                {WR,LOAD_IR,DATACTL_ENA,HALT}<=4'b0000;
                            end
             state<=4'b0110;
end
4'b0110:
      begin
         if(OPCODE==STO)                        
            begin
               {INC_PC,LOAD_ACC,LOAD_PC,RD}<=4'b0000;
               {WR,LOAD_IR,DATACTL_ENA,HALT}<=4'b0010;
            end
         else
             if(OPCODE==ADD||OPCODE==ANDD||OPCODE==XORR||OPCODE==LDA)
               begin
               {INC_PC,LOAD_ACC,LOAD_PC,RD}<=4'b0001;
               {WR,LOAD_IR,DATACTL_ENA,HALT}<=4'b0000;
               end
            else
              begin
              {INC_PC,LOAD_ACC,LOAD_PC,RD}<=4'b0000;
              {WR,LOAD_IR,DATACTL_ENA,HALT}<=4'b0000;
              end
        state<=4'b0111;
    end
    4'b0111:
       begin
         if(OPCODE==SKZ&&ZERO==1)
           begin
           {INC_PC,LOAD_ACC,LOAD_PC,RD}<=4'b1000;
           {WR,LOAD_IR,DATACTL_ENA,HALT}<=4'b0000; 
           end 
        else
          begin
          {INC_PC,LOAD_ACC,LOAD_PC,RD}<=4'b0000;
          {WR,LOAD_IR,DATACTL_ENA,HALT}<=4'b0000;
          end
          state<=4'b0000;
      end
      default:
      begin
          {INC_PC,LOAD_ACC,LOAD_PC,RD}<=4'b0000;
          {WR,LOAD_IR,DATACTL_ENA,HALT}<=4'b0000;
          state<=4'b0000;
      end
  endcase
  end
 endtask
 endmodule