clk_gen.v

verilog语言写的简单八位处理器。有8个模块

module clk_gen(CLK,RESET,CLK1,CLK2,CLK4,FETCH,ALU_CLK);
input CLK,RESET;
output CLK1,CLK2,CLK4,FETCH,ALU_CLK;
wire CLK,RESET;
reg CLK2,CLK4,FETCH,ALU_CLK;
reg[7:0] state;
parameter S1=8'b00000001,
          S2=8'b00000010,
          S3=8'b00000100,
          S4=8'b00001000,
          S5=8'b00010000,
          S6=8'b00100000,
          S7=8'b01000000,
          S8=8'b10000000,
        idle=8'b00000000;
        assign CLK1=~CLK;
        always@(negedge CLK)
           if(RESET)
                   begin
                       CLK2<=0;
                       CLK4<=1;
                       FETCH<=0;
                       ALU_CLK<=0;
                       state<=idle;
                end
            else 
                  begin
                      case(state)
                          S1:
                             begin
                                 CLK2<=~CLK2;
                                 ALU_CLK<=~ALU_CLK;
                                 state<=S2;
                              end
                        S2:
                           begin
                               CLK2<=~CLK2;
                               CLK4<=~CLK4;
                               ALU_CLK<=~ALU_CLK;
                               state<=S3;
                           end
                        S3:
                           begin
                               CLK2<=~CLK2;
                               state<=S4;
                           end
                        S4:
                           begin
                               CLK2<=~CLK2;
                               CLK4<=~CLK4;
                               FETCH<=~FETCH;
                               state<=S5;
                           end
                        S5:
                           begin
                               CLK2<=~CLK2;
                               state<=S6;
                           end
                        S6:
                           begin
                               CLK2<=~CLK2;
                               CLK4<=~CLK4;
                               state<=S7;
                           end
                        S7:
                           begin
                               CLK2<=~CLK2;
                               state<=S8;
                           end
                        S8:
                           begin
                               CLK2<=~CLK2;
                               CLK4<=~CLK4;
                               FETCH<=~FETCH;
                               state<=S1;
                           end
                        idle:   state<=S1;
                        default: state<=idle;
            endcase
    end
endmodule