leddisplay.v

使用Verilog语言编写的数字钟程序.有慢校时,快校时,闹钟等功能.

module leddisplay(inmin,insec,freq1k,reset,dataout,sl1,sl2,sl3,sl4);

input[15:0] inmin,insec;
input freq1k,reset;
output[7:0] dataout;
output sl1,sl2,sl3,sl4;

reg[1:0] count;
reg sl1,sl2,sl3,sl4;
reg[7:0] dataout;

always @ (posedge freq1k or negedge reset)
 begin
  if(reset==0)  
    begin
    dataout=8'hff;
    count=0;
    end
  else
    begin  
    if(count==0)
      begin
      dataout=insec[7:0];
      count=count+1;
      sl1=1;sl2=1;sl3=1;sl4=0;
      end
    else if(count==1)
     begin
     dataout=insec[15:8];
     count=count+1;
     sl1=1;sl2=1;sl3=0;sl4=1;
     end
    else if(count==2)
      begin
      dataout=inmin[7:0];
      count=count+1;
      sl1=1;sl2=0;sl3=1;sl4=1;
      end
    else 
      begin
      dataout=inmin[15:8];
      count=0;
      sl1=0;sl2=1;sl3=1;sl4=1;
      end
    end  
 end

endmodule