count12.v

来自「使用Verilog语言编写的数字钟程序.有慢校时,快校时,闹钟等功能.」· Verilog 代码 · 共 36 行

module count12 (clk,reset,out);

input clk,reset;
output[7:0] out;
//output cout;

reg[7:0] out;
//reg cout;

always @ (posedge clk or negedge reset)
begin
  if(reset==0)
    begin
    out=4'h0;
    //cout=1'b0;
    end
  else
    begin
    if(out[7:4]==4'h1)
       begin
       if(out[3:0]==4'h2)
          out[7:0]=8'h0;
       else out[3:0]=out[3:0]+1;
       end
    else 
      if(out[3:0]==4'h9)
       begin
       out[3:0]=4'h0;
       out[7:4]=4'h1;
       end        
      else     out[3:0]=out[3:0]+1;
    
    end
end
endmodule