devfreq1000.v

来自「使用Verilog语言编写的数字钟程序.有慢校时,快校时,闹钟等功能.」· Verilog 代码 · 共 23 行

module devfreq1000(in,reset,out);

input in,reset;
output out;
reg out;
reg[8:0] count;

always @ (posedge in or negedge reset)
  begin
    if(reset==0)
        begin
         count<=0;
         out<=0;
        end
    else
           if(count==9'h1ff)
                 begin 
                    count<=0;
                    out<=~out;
                 end
           else count<=count+1;
  end
endmodule